Pre-staged instruction registers for variable length instruction set machine

1. A processor comprising:

a memory;

at least one functional processing unit;

a bus coupled to the memory;

a set of instruction registers coupled to the bus and storing a set of pre-staged instructions from the memory; and

a logic circuit coupled to the set of instruction registers and the at least one functional processing unit to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the memory.

2. The processor of claim 1 , further comprising:

an interpreter block coupled to the memory;

wherein the interpreter block is configured to conduct a parse operation on a set of instructions;

wherein the parse operation identifies at least one redundancy; and

wherein the interpreter block is configured to write the instruction to the memory based on the parse operation and the at least one redundancy.

3. The processor of claim 2 , wherein:

the interpreter block is a hardware block.

4. The processor of claim 1 , further comprising:

a means for conducting a parsing operation on a set of instructions and writing the instruction to the memory based on the parsing operation;

wherein the means for conducting a parsing operation on a set of instructions and writing the instruction to the memory based on the parsing operation is a hardware block.

5. The processor of claim 1 , further comprising:

a core controller;

wherein the processor is a processing core; and

wherein the core controller is configured to load, using the bus, the set of pre-staged instructions from the memory to the set of instruction registers.

6. The processor of claim 1 , wherein:

the processor has an instruction set;

the bus is at least as wide as an instruction size of the instruction set;

the set of pre-staged instructions in the set of pre-staged instructions each have a size equal to the instruction size; and

the instruction has a size equal to the instruction size.

7. The processor of claim 1 , wherein:

the logic circuit includes an instruction decode logic circuit; and

the at least one functional processing unit and the instruction decode logic circuit execute instructions from the memory.

8. The processor of claim 1 , wherein the logic circuit comprises:

a shift register; and

a multiplexer that is control-coupled to the shift register;

wherein the logic circuit is configured to load the shift register with sequence information from the instruction; and

wherein the logic circuit is configured to, using the sequence information and the shift register, provide the set of pre-staged instructions from the set of instruction registers through the multiplexer to the at least one functional processing unit.

9. The processor of claim 8 , wherein:

the shift register is configured to shift when a set of designated dependencies have been satisfied.

10. The processor of claim 1 , wherein:

the instruction includes selection information and sequence information;

the logic circuit is configured to select, using the selection information, a subset of the set of pre-staged instructions; and

the logic circuit is configured to provide, in accordance with the sequence information, the subset of the set of pre-staged instructions to the at least one functional processing unit.

11. The processor of claim 1 , wherein:

the instruction includes sequence information; and

the logic circuit is configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit using the sequence information from the instruction.

12. The processor of claim 1 , further comprising:

a set of staging registers accessible to the at least one functional processing unit;

wherein the instruction includes configuration information;

wherein the logic circuit is configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit along with the configuration information; and

wherein the configuration information sets addresses in the set of staging registers to be used by the set of pre-staged instructions.

13. The processor of claim 1 , wherein:

the at least one functional processing unit includes at least two functional processing units; and

the logic circuit provides at least two pre-staged instructions from the set of pre-staged instructions to the at least two functional processing units in parallel.

14. The processor of claim 1 , wherein the logic circuit comprises:

at least two multiplexers controlled by at least two shift registers in a one-to-one correspondence;

wherein the logic circuit is configured to load the at least two shift registers with sequence information from the instruction;

wherein the at least one functional processing unit includes at least two functional processing units; and

wherein the logic circuit is configured to, using the sequence information and the at least two shift registers, provide the set of pre-staged instructions to the at least two functional processing units in parallel.

15. The processor of claim 1 , wherein:

the logic circuit comprises at least two multiplexers controlled by at least two shift registers in a one-to-one correspondence;

the at least one functional processing unit comprises at least two different functional blocks selected from: a load block, a data type conversion block, an arithmetic logic unit block, a floating-point math block, a rounding block, and a store block;

the logic circuit is configured to load the at least two shift registers with sequence information from the instruction; and

the logic circuit is configured to, using the sequence information in the at least two shift registers, provide the set of pre-staged instructions from the set of instruction registers through the at least two multiplexers to the at least one functional processing unit.

16. A method, in which each step is conducted by a processor, comprising:

storing a set of instructions in a memory;

loading a set of pre-staged instructions from the memory to a set of instruction registers;

receiving an instruction at a logic circuit; and

providing, in response to receiving the instruction and using the logic circuit, the set of instructions from the set of instruction registers to at least one functional processing unit.

17. The method of claim 16 , further comprising:

parsing, using an interpreter block and prior to storing the set of instructions in the memory, a sequence of instructions to identify at least one redundancy; and

writing the set of instructions to the memory based on the parsing and the at least one redundancy.

18. The method of claim 16 , further comprising:

loading, using the logic circuit, a shift register of the logic circuit with sequence information from the instruction;

controlling a multiplexer with the sequence information from the shift register; and

providing, through the multiplexer, the set of instructions from the set of instruction registers to the at least one functional processing unit.

19. The method of claim 18 , further comprising:

receiving a processor instruction fetch command; and

shifting the shift register upon receiving the processor instruction fetch command.

20. The method of claim 16 , wherein:

the at least one functional processing unit includes at least two functional processing units; and

the providing of the set of instructions from the set of instruction registers includes providing instructions to the at least two functional processing units in parallel.

21. The method of claim 16 , wherein:

the at least one functional processing unit comprise a load block and at least one different functional block; and

the instruction is a load instruction with dedicated space for additional sequence information to define how the set of pre-staged instructions are executed.

22. A processor comprising:

a memory;

at least one functional processing unit;

a bus;

a set of instruction registers;

a means for conducting a parsing operation on a set of instructions stored in the memory, identifying at least one redundancy, and writing an instruction to the memory based on the parsing operation;

a means for loading the set of instruction registers with a set of pre-staged instructions using the bus; and

a means for providing the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving the instruction from the memory.