IP Library Granted Patent US 12,470,216
Granted Patent B2
US 12,470,216 · App. 18/099,174 · Granted Nov 11, 2025

System and method for configuring programmable analog block

Inventors: Nidhin Mulangattil Sudhakaran (Lynnwood, WA); Bert Sullam (Bellevue, WA); Eashwar Thiagarajan (Bothell, WA)
Assignee: Cypress Semiconductor Corporation
H03K19/017581H03F3/45668H03K19/17744
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Quick Facts
Patent No.
US 12,470,216
App. No.
18/099,174
Granted
Nov 11, 2025
Kind
B2
Abstract

One or more computing devices, systems, and/or methods are provided. In an example of the techniques presented herein, a system comprises a first input terminal and a first programmable analog block configured according to a first configuration. A controller is configured to reconfigure the first programmable analog block according to a second configuration different than the first configuration based on a first signal received at the first input terminal.

Claims (73)

1 . A system, comprising:

a central processing unit; and

a programmable analog sub-system connected to the central processing unit and comprising:

a first input terminal;

a first programmable analog block configured according to a first configuration; and

a controller configured to reconfigure the first programmable analog block according to a second configuration different than the first configuration based on a first signal received at the first input terminal independent from the central processing unit.

2 . The system of claim 1 , wherein:

the central processing unit and the programmable analog block are on a single semiconductor die.

3 . The system of claim 1 , comprising:

a second input terminal, wherein:

the programmable analog block comprises:

a first operational amplifier; and

routing circuitry selectively connecting the first input terminal or the second input terminal to a first terminal of the first operational amplifier.

4 . The system of claim 3 , wherein:

the routing circuitry is configured to selectively connect one of a first reference signal or a second reference signal to a second terminal of the first operational amplifier.

5 . The system of claim 3 , wherein:

in the first configuration, the first input terminal is connected by the routing circuitry to the first terminal of the first operational amplifier; and

in the second configuration, the second input terminal is connected by the routing circuitry to the first terminal of the first operational amplifier.

6 . The system of claim 5 , wherein:

the first input terminal is connected to a photodiode; and

the second input terminal is connected to a microphone.

7 . The system of claim 5 , wherein:

the first input terminal is connected to one of a photodiode or a microphone; and

the second input terminal is connected to an electrocardiogram sensor.

8 . The system of claim 2 , wherein:

in the first configuration, the first programmable analog block is configured to receive the first signal at the first terminal of the first operational amplifier and generate an output signal; and

the controller is configured to reconfigure the first programmable analog block according to the second configuration based on the output signal.

9 . The system of claim 1 , comprising:

a second programmable analog block configured according to a third configuration, wherein:

in the third configuration, the second programmable analog block is configured to receive the first signal and generate an output signal; and

the controller is configured to reconfigure the first programmable analog block according to the second configuration based on the output signal.

10 . The system of claim 9 , wherein:

the controller is configured to reconfigure the second programmable analog block according to a fourth configuration different than the third configuration based on the first signal.

11 . A programmable analog subsystem, comprising:

a first operational amplifier;

first routing circuitry configured to connect the first operational amplifier to a first input terminal in a first configuration and to connect the first operational amplifier to a second input terminal in a second configuration;

second routing circuitry configured to connect one of a first reference signal or a second reference signal to the first operational amplifier in the first configuration or the second configuration; and

a controller configured to receive an output signal of the first operational amplifier in the first configuration and reconfigure the first routing circuitry or the second routing circuitry based on the output signal.

12 . The programmable analog subsystem of claim 11 , comprising:

a second operational amplifier; and

a switch connecting the first operational amplifier to the second operational amplifier.

13 . The programmable analog subsystem of claim 11 , comprising:

a programmable resistor connected to the first operational amplifier; and

third routing circuitry configured to connect one of a first reference signal, a second reference signal, or an output of a second programmable analog block to the programmable resistor.

14 . The programmable analog subsystem of claim 13 , wherein the programmable resistor comprises:

a first resistor;

a second resistor connected to the first resistor at a node; and

a switch connected between the node and the first operational amplifier.

15 . The programmable analog subsystem of claim 11 , comprising:

a switch connected between an output of the first operational amplifier and an output terminal.

16 . A method, comprising:

configuring a first programmable analog block according to a first configuration;

configuring a second programmable analog block according to a second configuration;

receiving a first input signal at the first programmable analog block;

generating a first output signal based on the first input signal received at the first programmable analog block; and

reconfiguring one of the first programmable analog block or the second programmable analog block according to a third configuration based on the first output signal without intervention from an external central processing unit.

17 . The method of claim 16 , wherein reconfiguring one of the first programmable analog block or the second programmable analog block according to the third configuration comprises:

reconfiguring the first programmable analog block to receive a second input signal; and

generating a second output signal based on the second input signal received at the first programmable analog block.

18 . The method of claim 16 , comprising:

receiving a second input signal at the second programmable analog block; and

generating a second output signal based on the second input signal received at the second programmable analog block, wherein:

reconfiguring one of the first programmable analog block or the second programmable analog block according to the third configuration comprises:

reconfiguring the second programmable analog block to receive a third input signal; and

generating a third output signal based on the third input signal received at the second programmable analog block.

19 . The method of claim 18 , wherein:

receiving the first input signal comprises receiving a first audio signal;

receiving the second input signal comprises receiving an optical signal; and

receiving the third input signal comprises receiving a second audio signal.

20 . The method of claim 16 , wherein:

receiving the first input signal comprises receiving a first optical signal;

generating the first output signal comprises generating a heart rate signal; and

reconfiguring one of the first programmable analog block or the second programmable analog block comprises reconfiguring the first programmable analog block or the second programmable analog block to process an electrocardiogram signal.

Assignments (3)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
MERGER AND CHANGE OF NAME Recorded Oct 21, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION; INFINEON TECHNOLOGIES AMERICAS CORP.
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073140/0554 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2023
From: SUDHAKARAN, NIHDIN MULANGATTIL; SULLAM, BERT; THIAGARAJAN, EASHWAR
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 063050/0406 →
Continuity (1)
Related Publication 20240250684A1 · Jul 25, 2024
References Cited (4)
US 8547135B1 · Yarlagadda · 2013 [cited by examiner]
US 8717070B1 · Klein · 2014 [cited by examiner]
US 9473144B1 · Thiagarajan · 2016 [cited by examiner]
US 20160065216A1 · Thiagarajan · 2016 [cited by examiner]