3D memory circuit
Some embodiments provide a three-dimensional (3D) circuit that has data lines of one or more memory circuits on a different IC die than the IC die(s) on which the memory blocks of the memory circuit(s) are defined. In some embodiments, the 3D circuit includes a first IC die with a first set of two or more memory blocks that have a first set of data lines. The 3D circuit also includes a second IC die that is stacked with the first IC dies and that includes a second set of two or more memory blocks with a second set of data lines. The 3D circuit further includes a third IC die that is stacked with the first and second IC dies and that includes a third set of data lines, which connect through several z-axis connections with the first and second sets of data lines to carry data to and from the first and second memory block sets when data is being written to and read from the first and second memory block sets. The z-axis connections in some embodiments electrically connect circuit nodes in overlapping portions of the first and third IC dies, and overlapping portions of second and third IC dies, in order to carry data between the third set of data lines on the third IC die and the first and second set of data lines of the first and second of memory block sets on the first and second IC dies. These z-axis connections between the dies are very short as the dies are very thin. For instance, in some embodiments, the z-axis connections are less than 10 or 20 microns. The z-axis connections are through silicon vias (TSVs) in some embodiments.
1. A device comprising:
an integrated circuit (IC) die stack comprising a first die and a plurality of second die, wherein:
the first die comprises global data lines, global input/output (I/O) circuits, and processing cores;
each of the plurality of second die comprises:
memory blocks,
local data lines connected to the memory blocks,
an addressing circuit, and
a local input/output (I/O) circuit;
an active side of the first die is directly bonded to a topmost second die of the plurality of second die;
the local data lines of the topmost second die of the plurality of second die are communicatively coupled to the global data lines of the first die;
the processing cores are capable of receiving, through the global I/O circuits, data from the memory blocks and providing, through the global I/O circuits, data to the memory blocks;
each addressing circuit is capable of activating different memory blocks of the respective second die; and
each local input/output (I/O) circuit is capable of writing/reading data to the respective activated memory blocks.
2. The device of claim 1 , wherein the global data lines of the first die vertically overlap the local data lines of the topmost second die of the plurality of second die.
3. The device of claim 1 , wherein the first die further comprises a multiplexer between the I/O circuits and the processing cores, and the multiplexer is capable of connecting different subsets of the global data lines with the processing cores at different times.
4. The device of claim 1 , wherein the active side of the first die is hybrid bonded to the topmost second die of the plurality of second die.
5. The device of claim 1 , wherein local data lines of each of the plurality of second die vertically overlap with respective local data lines of one or more adjacent second die.
6. The device of claim 5 , wherein the vertically overlapping local data lines are connected through hybrid bonds formed between adjacent ones of the second die.
7. The device of claim 1 , wherein memory blocks of each of the plurality of second die vertically overlap with respective memory blocks of one or more adjacent second die.
8. The device of claim 7 , wherein each global data line is connected to a respective plurality of overlapping memory blocks.
9. The device of claim 7 , wherein:
local data lines of each of the plurality of second die vertically overlap with respective local data lines of one or more adjacent second die;
the vertically overlapping local data lines are connected through hybrid bonds formed between adjacent ones of the second die; and
each global data line is connected to a respective plurality of overlapping memory blocks through a corresponding plurality of overlapping local data lines.
10. The device of claim 1 , wherein each of the plurality of second die comprises pass gate controls capable of connecting each local data line to a respective global data line.
11. The device of claim 1 , wherein each of the memory blocks is connected to complimentary local data lines.
12. The device of claim 11 , wherein the complimentary local data lines are connected to a differential sense amplifier circuit.
13. The device of claim 11 , wherein the complimentary local data lines are connected to a respective global data line through a pass gate control.
14. The device of claim 1 , wherein at least some of the local data lines are connected to respective global data lines by TSVs disposed through one or more of the second die.
15. The device of claim 14 , wherein one or more of the second die have a TSV density of more than 100,000,000 per square centimeter.
16. The device of claim 1 , wherein the IC die stack is capable of reading from and/or writing to memory blocks on each respective second die in parallel.
17. The device of claim 1 , wherein the global data lines provide parallel read/write access to respective memory blocks on each second die.
18. The device of claim 1 , wherein:
the addressing circuits of each second die are capable of activating different addressed locations in the memory blocks;
the first die further comprises input/output (I/O) circuits capable of reading data from and writing data to the memory blocks of each second die; and
the respective memory blocks and addressing circuits of the second die and I/O circuits of the first die connected thereto collectively form a plurality of memory circuits.
19. The device of claim 1 , wherein each memory block comprises logical storage cells, and each logical storage cell is connected to a bit line and a word line.
20. A device comprising:
an integrated circuit (IC) die stack comprising a first die and a plurality of second die, wherein:
the first die comprises global data lines, global input/output (I/O) circuits, and processing cores;
each of the plurality of second die comprises:
memory blocks,
local data lines connected to the memory blocks,
an addressing circuit, and
a local input/output (I/O) circuit;
an active side of the first die is directly bonded to a topmost second die;
the local data lines of the topmost second die are communicatively coupled to the global data lines of the first die;
the processing cores are capable of receiving, through the global I/O circuits, data from the memory blocks and providing, through the global I/O circuits, data to the memory blocks;
each addressing circuit is capable of activating different memory blocks of the respective second die;
each local input/output (I/O) circuit is capable of writing/reading data to the respective activated memory blocks; and
wherein the processing cores implement machine-trained nodes of a machine trained network.