Integrated circuit interconnect shape optimizer
Systems, devices, and methods for optimization of conducting interconnects are described. A method includes receiving an integrated circuit layout including a plurality of terminals and an interconnect, wherein the interconnect represents a conductive coupling between the plurality of terminals. The method includes receiving terminal information describing operating parameters of the plurality of terminals. The method includes receiving layer information describing material composition and material property information for the plurality of terminals and the interconnect. The method includes generating a three-dimensional representation of an integrated circuit using the integrated circuit layout and the layer information. The method includes determining an individual contribution of a cell included in the three-dimensional representation to a resistance-capacitance (RC) value of the interconnect using the three-dimensional representation and the terminal information. The method also includes generating an updated integrated circuit layout based at least in part on the individual contribution.
1 . A computer-implemented method for optimization of conducting interconnects, the method comprising:
receiving an integrated circuit layout including a plurality of terminals and an interconnect, wherein the interconnect represents a conductive coupling between the plurality of terminals;
receiving terminal information describing operating parameters of the plurality of terminals;
receiving layer information describing material composition and material property information for the plurality of terminals and the interconnect;
generating a three-dimensional representation of an integrated circuit using the integrated circuit layout and the layer information, wherein the three-dimensional representation includes a cell corresponding to a discrete volumetric element of the three-dimensional representation, the cell representing at least a portion of the interconnect or at least a portion of a non-conducting material external to the interconnect;
determining an individual contribution of the cell to a resistance-capacitance (RC) value of the interconnect using the three-dimensional representation and the terminal information; and
generating an updated integrated circuit layout based at least in part on the individual contribution.
2 . The computer-implemented method of claim 1 , wherein determining the individual contribution of the element to the RC value comprises:
determining a generator admittance and a load admittance for the cell based at least in part on the layer information and the terminal information;
determining an input admittance using the generator admittance and the load admittance;
determining an admittance density for the cell using the input admittance, wherein the admittance density describes a local contribution of the cell to an admittance of the interconnect; and
generating a differential RC value for the cell based at least in part on the admittance density.
3 . The computer-implemented method of claim 1 , wherein the cell is a first cell, wherein the three-dimensional representation further includes a second cell, and wherein generating the updated integrated circuit layout comprises:
determining conductive contributions of the first cell and the second cell to a conductance of the interconnect;
determining capacitive contributions of the first cell and the second cell to a capacitance of the interconnect;
generating a smoothed conductive contribution and a smoothed capacitive contribution for the first cell using the respective contributions of the first cell and the second cell; and
determining a material composition for the first cell based at least in part on the smoothed contributions for the first cell.
4 . The computer-implemented method of claim 3 , wherein determining the material composition comprises:
when the cell represents a part of the interconnect, re-assigning the cell to represent the non-conducting material if the smoothed capacitive contribution for the first cell exceeds the smoothed conductive contribution of the first cell; or
when the cell represents a part of the non-conducting material, re-assigning the cell to represent the interconnect if the smoothed conductive contribution for the first cell exceeds the smoothed capacitive contribution of the first cell.
5 . The computer-implemented method of claim 4 , wherein generating the smoothed contributions for the first cell comprises three-dimensional smoothing of the respective contributions of the first cell and the second cell.
6 . The computer-implemented method of claim 4 , wherein generating the smoothed contributions for the first cell comprises gaussian smoothing using a standard deviation parameter, σ, less than a width of the interconnect in the integrated circuit layout.
7 . The computer-implemented method of claim 1 , further comprising:
inputting the updated integrated circuit layout to a process model configured to output a simulated manufactured integrated circuit produced by a semiconductor manufacturing system using the updated integrated circuit layout;
generating the simulated manufactured integrated circuit as the output of the process model; and
determining a manufacturability of the updated integrated circuit layout for the semiconductor manufacturing system using the output of the process model.
8 . The computer-implemented method of claim 7 , wherein the manufacturability indicates that the updated integrated circuit layout is not manufacturable by the semiconductor manufacturing system, the method further comprising:
generating a revised layout using the updated integrated circuit layout and the process model, the revised layout being manufacturable by the semiconductor manufacturing system.
9 . The computer-implemented method of claim 1 , wherein the plurality of terminals comprises an input terminal and two output terminals.
10 . The computer-implemented method of claim 1 , wherein the plurality of terminals comprises a plurality of input terminals and at least one output terminal, wherein the three-dimensional representation is a first representation, and wherein the method further comprises:
generating the first representation corresponding to when a first input terminal included in the input terminals is active and remaining input terminals are inactive;
generating a second representation using the integrated circuit layout and the layer information, the second representation corresponding to when a second input terminal included in the input terminals is active and remaining input terminals are inactive, and wherein both the first representation and the second representation include the cell;
generating a first partial update using the first representation;
generating a second partial update using the second representation; and
generating the updated integrated circuit layout using the first partial update and the second partial update.
11 . The computer-implemented method of claim 10 , wherein generating the updated integrated circuit layout comprises merging the first partial update and the second partial update using an inclusive OR operator.
12 . The computer-implemented method of claim 1 , further comprising outputting the updated integrated circuit layout, the outputting comprising:
generating an updated integrated circuit layout file using the updated integrated circuit layout; and
storing the updated integrated circuit layout file in a data store.
13 . A non-transitory computer readable memory device storing machine-executable instructions that, when executed by a machine, cause the machine to perform operations comprising:
receiving an integrated circuit layout including a plurality of terminals and an interconnect, wherein the interconnect represents a conductive coupling between the plurality of terminals;
receiving terminal information describing operating parameters of the plurality of terminals;
receiving layer information describing material composition and material property information for the plurality of terminals and the interconnect;
generating a three-dimensional representation of an integrated circuit using the integrated circuit layout and the layer information, wherein the three-dimensional representation includes a cell corresponding to a discrete volumetric element of the three-dimensional representation, the cell representing at least a portion of the interconnect or at least a portion of a non-conducting material external to the interconnect;
determining an individual contribution of the cell to a resistance-capacitance (RC) value of the interconnect using the three-dimensional representation and the terminal information; and
generating an updated integrated circuit layout based at least in part on the individual contribution.
14 . The non-transitory computer readable memory device of claim 13 , wherein determining the individual contribution of the element to the RC value comprises:
determining a generator admittance and a load admittance for the cell based at least in part on the layer information and the terminal information;
determining an input admittance using the generator admittance and the load admittance;
determining an admittance density for the cell using the input admittance, wherein the admittance density describes a local contribution of the cell to an admittance of the interconnect; and
generating a differential RC value for the cell based at least in part on the admittance density.
15 . The non-transitory computer readable memory device of claim 13 , wherein the three-dimensional representation further includes a second cell, and wherein generating the updated integrated circuit layout comprises:
determining conductive contributions of the first cell and the second cell to a conductance of the interconnect;
determining capacitive contributions of the first cell and the second cell to a capacitance of the interconnect;
generating a smoothed conductive contribution and a smoothed capacitive contribution for the first cell using the respective contributions of the first cell and the second cell; and
determining a material composition for the first cell based at least in part on the smoothed contributions for the first cell.
16 . The non-transitory computer readable memory device of claim 15 , wherein determining the material composition comprises:
when the cell represents a part of the interconnect, re-assigning the cell to represent the non-conducting material if the smoothed capacitive contribution for the first cell exceeds the smoothed conductive contribution of the first cell; or
when the cell represents a part of the non-conducting material, re-assigning the cell to represent the interconnect if the smoothed conductive contribution for the first cell exceeds the smoothed capacitive contribution of the first cell.
17 . The non-transitory computer readable memory device of claim 13 , wherein generating the smoothed contributions for the first cell comprises gaussian smoothing using a standard deviation parameter, σ, less than an initial width of the interconnect in the integrated circuit layout.
18 . The non-transitory computer readable memory device of claim 13 , wherein the instructions, when executed by the machine, cause the machine to perform further operations comprising:
inputting the updated integrated circuit layout to a process model configured to output a simulated manufactured integrated circuit produced by a semiconductor manufacturing system using the updated integrated circuit layout;
generating the simulated manufactured integrated circuit as the output of the process model; and
determining a manufacturability of the updated integrated circuit layout for the semiconductor manufacturing system based at least in part on the output of the process model.
19 . The non-transitory computer readable memory device of claim 18 , wherein the manufacturability indicates that the updated integrated circuit layout is not manufacturable by the semiconductor manufacturing system, and wherein the instructions, when executed by the machine, cause the machine to perform further operations comprising:
generating a revised layout based at least in part on the updated integrated circuit layout and the process model, the revised layout being manufacturable by the semiconductor manufacturing system.
20 . The non-transitory computer readable memory device of claim 13 , wherein the plurality of terminals comprises a plurality of input terminals and at least one output terminal, wherein the three-dimensional representation is a first representation, and wherein the instructions, when executed by the machine, cause the machine to perform further operations comprising:
generating the first representation corresponding to when a first input terminal included in the input terminals is active and remaining input terminals are inactive;
generating a second representation using the integrated circuit layout and the layer information, the second representation corresponding to when a second input terminal included in the input terminals is active and remaining input terminals are inactive, and wherein both the first representation and the second representation include the cell;
generating a first partial update using the first representation;
generating a second partial update using the second representation; and
generating the updated integrated circuit layout using the first partial update and the second partial update.