Nonvolatile memory device including dual memory layers
The present invention is directed to a nonvolatile memory device including a plurality of first conductive lines extending along a first direction; first and second plurality of second conductive lines extending along a second direction; an array of active regions, each active region having an elongated shape directed along a third direction substantially bisecting an angle formed between the first and second directions and including first and second drains formed at opposite ends thereof; and an array of first memory elements and an array of second memory elements formed at different levels, each first memory element and each second memory element being electrically connected to a respective first drain and a respective second drain, respectively. The first and second plurality of second conductive lines are electrically connected to the array of first memory elements and the array of second memory elements along the second direction, respectively.
1. A nonvolatile memory device comprising:
a plurality of first conductive lines extending along a first direction;
first and second plurality of second conductive lines extending along a second direction;
an array of active regions, each active region having an elongated shape directed along a third direction substantially bisecting an angle formed between the first and second directions and including first and second drains formed at opposite ends of each active region along the third direction; and
an array of first memory elements and an array of second memory elements formed at different levels with respect to the array of active regions, each first memory element and each second memory element being electrically connected to a respective first drain and a respective second drain, respectively,
wherein the first and second plurality of second conductive lines are electrically connected to the array of first memory elements and the array of second memory elements along the second direction, respectively.
2. The nonvolatile memory device of claim 1 , wherein the second direction is substantially perpendicular to the first direction.
3. The nonvolatile memory device of claim 1 , wherein each active region includes two of a plurality of selection transistors sharing one of a plurality of common sources formed between the first and second drains.
4. The nonvolatile memory device of claim 3 , wherein the plurality of first conductive lines cross the array of active regions and are configured to control current flow in the plurality of selection transistors.
5. The nonvolatile memory device of claim 3 , wherein one of the two of the plurality of selection transistors includes the first drain and the other one of the two of the plurality of selection transistors includes the second drain.
6. The nonvolatile memory device of claim 3 further comprising a plurality of third conductive lines electrically connected to the plurality of common sources along the second direction.
7. The nonvolatile memory device of claim 1 , wherein the first and second plurality of second conductive lines are coplanar.
8. The nonvolatile memory device of claim 1 , wherein the array of first memory elements and the array of second memory elements have different switching mechanisms.
9. The nonvolatile memory device of claim 1 , wherein the array of first memory elements and the array of second memory elements comprise magnetic tunnel junctions.
10. The nonvolatile memory device of claim 9 , wherein the array of first memory elements and the array of second memory elements have different structures.