Image sensor with stacked CCD and CMOS architecture
Image sensor systems are disclosed that include charge coupled device (CCD) pixels integrated with CMOS readout circuitry via separately bonded substrates. According to some embodiments, columns of image sensing pixels on a first substrate are arranged with overlapping gate structures to facilitate charge transfer between the pixels. At least one pixel is coupled to a first conductive pad that contacts (or is melded with) a second conductive pad from a second substrate bonded to the first substrate. The second substrate includes a readout circuit using one or more CMOS devices coupled to the second conductive pad to receive the accumulated charge from a given column of pixels. The resulting photodetector signal from the accumulated charge can be, for instance, amplified via a source follower component and ultimately read out to a column amplifier, and subjected to further processing and/or use in a given downstream system.
1. An image sensor, comprising:
an array of image sensing pixels on a first substrate, wherein at least one image sensing pixel comprises a gate over the first substrate, and wherein an adjacent gate from an adjacent image sensing pixel partially overlaps with the gate of the at least one image sensing pixel;
a conductive structure on the first substrate and coupled to a given pixel of the array of image sensing pixels;
a readout circuit coupled to the conductive structure, wherein the readout circuit comprises one or more metal oxide semiconductor (MOS) devices on a second substrate different from the first substrate; and
a dielectric layer between the gate of the at least one image sensing pixel and the first substrate, wherein the dielectric layer has a thickness between about 10 nm and about 100 nm.
2. The image sensor of claim 1 , further comprising one or more reset gates coupled to at least one of the image sensing pixels.
3. The image sensor of claim 1 , wherein the conductive structure comprises a first conductive pad on the first substrate and a second conductive pad on the second substrate.
4. The image sensor of claim 1 , wherein the conductive structure has a cross-sectional area of less than 1 μm 2 .
5. The image sensor of claim 1 , wherein an overlap gap between the gate of the at least one image sensing pixel and the adjacent gate of the adjacent image sensing pixel is between about 10 nm and about 100 nm.
6. The image sensor of claim 1 , wherein the array of image sensing pixels comprises a plurality of columns of image sensing pixels, wherein each column of image sensing pixels on the first substrate is coupled to a corresponding conductive structure and each corresponding conductive structure is coupled to a corresponding readout circuit on the second substrate.
7. An image sensor, comprising:
a pixel array on a first substrate and having at least one column of image sensing pixels, wherein the at least one column of pixels includes at least a first pixel having a first gate over a semiconductor layer and a second pixel having a second gate over the semiconductor layer, wherein the first gate partially overlaps with the second gate;
a conductive structure coupled to at least one pixel of the column of pixels;
a readout circuit coupled to the conductive structure and on a second substrate different from the first substrate;
a column amplifier coupled to the readout circuit;
a dielectric layer between the first gate and the semiconductor layer and between the second gate and the semiconductor layer, wherein the dielectric layer has a thickness between about 10 nm and about 100 nm;
an analog-to-digital converter (ADC) coupled to the column amplifier; and
a processor coupled to the ADC.
8. The image sensor of claim 7 , further comprising one or more reset gates coupled to at least one of the image sensing pixels.
9. The image sensor of claim 7 , wherein the conductive structure comprises a first conductive pad on the first substrate and a second conductive pad on the second substrate.
10. The image sensor of claim 7 , wherein the first gate, the second gate, and the semiconductor layer are doped with n-type dopants.
11. The image sensor of claim 7 , wherein an overlap gap between the first gate and the second gate is between about 10 nm and about 100 nm.
12. An image sensor, comprising:
a first substrate having an array of image sensing pixels, wherein the array of image sensing pixels comprises a first pixel having a first gate and an adjacent second pixel having a second gate, and wherein the first gate partially overlaps with the second gate, wherein the first gate and the second gate are both over a common semiconductor layer;
a second substrate having a readout circuit that comprises one or more metal oxide semiconductor (MOS) devices;
a conductive structure that contacts at least a portion of the first substrate and at least a portion of the second substrate, wherein the conductive contact is coupled to an image sensing pixel of the array of image sensing pixels and is coupled to the readout circuit; and
a dielectric layer between the first gate and the common semiconductor layer and between the second gate and the common semiconductor layer, wherein the dielectric layer has a thickness between about 10 nm and about 100 nm.
13. The image sensor of claim 12 , wherein the conductive structure comprises a first conductive pad on the first substrate and a second conductive pad on the second substrate.
14. The image sensor of claim 12 , wherein the conductive structure has a cross-sectional area of less than 1 μm 2 .
15. The image sensor of claim 12 , wherein an overlap gap between the first gate and the second gate is between about 10 nm and about 100 nm.
16. The image sensor of claim 12 , wherein the array of image sensing pixels comprises a plurality of columns of image sensing pixels, wherein each column of image sensing pixels on the first substrate is coupled to a corresponding conductive structure and each corresponding conductive structure is coupled to a corresponding readout circuit on the second substrate.