VERTICAL FIN-BASED FIELD EFFECT TRANSISTOR (FINFET) WITH VARYING CONDUCTIVITY REGIONS
A vertical fin-based field effect transistor (FinFET) includes an array of FinFETs comprising a plurality of rows and columns of active fins with source contacts and one or more rows of first inactive fins disposed on a first set of sides of the array of FinFETs. The vertical FinFET also includes one or more columns of second inactive fins disposed on a second set of sides of the array of FinFETs. The first inactive fins and the second inactive fins are characterized by a reduced electrical conductivity compared to an electrical conductivity of the active fins of the array of FinFETs. The vertical FinFET further includes an active gate region surrounding the FinFETs of the array of FinFETs and an additional gate region surrounding the first inactive fins and the second inactive fins. At least a portion of the additional gate region is a neutralized gate region.
1 . A vertical fin-based field effect transistor (FinFET) device comprising:
an array of FinFETs comprising a plurality of rows and columns of active fins with source contacts;
one or more rows of first inactive fins disposed on a first set of sides of the array of FinFETs;
one or more columns of second inactive fins disposed on a second set of sides of the array of FinFETs, wherein the first inactive fins and the second inactive fins are characterized by a reduced electrical conductivity compared to an electrical conductivity of the active fins of the array of FinFETs;
an active gate region surrounding the FinFETs of the array of FinFETs; and
an additional gate region surrounding the first inactive fins and the second inactive fins, wherein at least a portion of the additional gate region is a neutralized gate region.
2 . The vertical FinFET device of claim 1 , wherein the first inactive fins and the second inactive fins comprise ion implanted fins.
3 . The vertical FinFET device of claim 1 , wherein the reduced electrical conductivity is reduced by at least 90%.
4 . The vertical FinFET device of claim 3 , wherein the reduced electrical conductivity is reduced by at least 99%.
5 . The vertical FinFET device of claim 1 , wherein the neutralized gate region is characterized by a second reduced electrical conductivity compared to a second electrical conductivity of the active gate region.
6 . The vertical FinFET device of claim 5 , wherein the neutralized gate region comprises an ion implanted gate region.
7 . The vertical FinFET device of claim 5 , wherein the second reduced electrical conductivity is reduced by at least 90%.
8 . The vertical FinFET device of claim 7 , wherein the second reduced electrical conductivity is reduced by at least 99%.
9 . The vertical FinFET device of claim 1 , wherein the additional gate region is the neutralized gate region.
10 . The vertical FinFET device of claim 1 , wherein the active fins, the first inactive fins, and the second inactive fins comprise a III-N semiconductor.
11 . A method of fabricating a transistor array, the method comprising:
forming an array of FinFETs comprising a plurality of rows and columns of active fins with source contacts, wherein each of the active fins is surrounded by an active gate region;
forming one or more rows of first inactive fins disposed on a first set of sides of the array of FinFETs, wherein each of the first inactive fins is surrounded by an additional gate region; and
forming one or more columns of second inactive fins disposed on a second set of sides of the array of FinFETs, wherein each of the second inactive fins is surrounded by the additional gate region;
forming a neutralization mask having openings exposing the first inactive fins, the second inactive fins, and a portion of the additional gate region; and
reducing an electrical conductivity of the first inactive fins, the second inactive fins, and the portion of the additional gate region.
12 . The method of claim 11 , wherein reducing the electrical conductivity comprises ion implanting a dopant into the first inactive fins, the second inactive fins, and the portion of the additional gate region.
13 . The method of claim 11 , wherein reducing the electrical conductivity comprises performing a hydrogen plasma treatment process on the first inactive fins, the second inactive fins, and the portion of the additional gate region.
14 . The method of claim 11 , wherein reducing the electrical conductivity comprises reducing the electrical conductivity by at least 90%.
15 . The method of claim 14 , wherein reducing the electrical conductivity comprises reducing the electrical conductivity by at least 99%.
16 . The method of claim 11 , wherein a portion of the additional gate region is the additional gate region.
17 . The method of claim 11 , further comprising providing a III-N substrate structure comprising:
providing a III-nitride substrate;
epitaxially growing a first III-nitride layer coupled to the III-nitride substrate; and
epitaxially growing a second III-nitride layer coupled to the first III-nitride layer.
18 . The method of claim 3 , wherein forming the array of FinFETs comprises:
forming a hard mask layer on the second III-nitride layer; and
patterning the hard mask layer to form a patterned hard mask.
19 . The method of claim 18 , wherein forming the array of FinFETs further comprises:
etching the second III-nitride layer and a portion of the first III-nitride layer using the patterned hard mask to form a plurality of trenches; and
selectively regrowing a third III-nitride layer in the plurality of trenches.
20 . The method of claim 3 , wherein:
the active fins are characterized by a first electrical conductivity; and
the first inactive fins and the second inactive fins are characterized by a second electrical conductivity less than the first electrical conductivity.