IP Library Granted Patent US 12,640,593
Granted Patent B2
US 12,640,593 · App. 18/108,928 · Granted May 26, 2026

Wake-up receiver

Inventors: Darshan Bhaskar Shetty (Graz, AT); Christoph Steffan (Marchtrenk, AT); Gerald Holweg (Graz, AT)
Assignee: Infineon Technologies Americas Corp.
H02J50/27G16Y40/35H01Q7/00H02J50/001H03K17/56
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Quick Facts
Patent No.
US 12,640,593
App. No.
18/108,928
Granted
May 26, 2026
Kind
B2
Abstract

One or more devices, systems, and/or methods are provided. In an example of the techniques presented herein, a wake-up receiver includes a power management unit configured to receive a supply voltage generated from an input signal and generate a current reference. An envelope detector is configured to generate a signal corresponding to transitions in the input signal. A signal processing unit is configured to generate an interrupt signal responsive to detecting a wake-up pattern in the signal from the envelope detector. The envelope detector comprises a first diode threshold compensated by the current reference.

Claims (76)

1 . A wake-up receiver, comprising:

a power management unit configured to receive a supply voltage generated from an input signal and generate a bias current;

an envelope detector comprising a first diode, wherein the first diode is threshold compensated by the bias current and configured to generate a signal corresponding to transitions in the input signal; and

a signal processing unit configured to generate an interrupt signal responsive to detecting a wake-up pattern in the signal from the envelope detector.

2 . The wake-up receiver of claim 1 , comprising:

an energy harvester configured to generate the supply voltage based on the input signal.

3 . The wake-up receiver of claim 1 , wherein the first diode comprises:

a compensation transistor having a first gate, a first input, and a first output connected to the first gate;

a rectification transistor having a second gate and a second output connected to the first input; and

a current source connected to the first gate and the second gate and configured to generate the bias current.

4 . The wake-up receiver of claim 3 , wherein the rectification transistor comprises:

a first transistor; and

a second transistor connected in parallel with the first transistor.

5 . The wake-up receiver of claim 3 , wherein the compensation transistor comprises:

a first transistor; and

a second transistor connected to the first transistor.

6 . The wake-up receiver of claim 5 , wherein the second transistor is connected in series with the first transistor.

7 . The wake-up receiver of claim 3 , wherein the rectification transistor and the compensation transistor comprise p-type transistors.

8 . The wake-up receiver of claim 1 , wherein the envelope detector comprises:

a first capacitor connected in parallel with the first diode; and

a current source configured to generate an integer multiple of the bias current connected in parallel with the first diode.

9 . The wake-up receiver of claim 8 , wherein the envelope detector comprises:

a second diode, wherein the second diode is threshold compensated by the bias current;

a second capacitor connected in parallel with the second diode; and

a voltage divider connected in parallel with the second diode.

10 . A system, comprising:

a radio frequency to direct current (RF-DC) converter comprising a first diode threshold, wherein the first diode is compensated by a bias current and configured to generate a supply voltage based on an RF input signal;

a power management unit configured to receive the supply voltage and generate the bias current;

an envelope detector comprising a second diode, wherein the second diode is threshold compensated by the bias current and configured to generate a signal corresponding to transitions in the RF input signal; and

a signal processing unit configured to generate an interrupt signal responsive to detecting a wake-up pattern in the signal from the envelope detector.

11 . The system of claim 10 , comprising:

a storage unit configured to store energy; and

a power on reset unit configured to operate the system in a first mode responsive to the supply voltage generated by the RF-DC converter exceeding a minimum voltage to allow receipt of data in the RF input signal and operate the system in a second mode responsive to the supply voltage generated by the RF-DC converter being sufficient to charge the storage unit.

12 . The system of claim 10 , comprising:

a small loop antenna connected to the RF-DC converter and the envelope detector.

13 . The system of claim 10 , wherein the first diode comprises:

a diode connected compensation transistor having a first gate and a first output;

a rectification transistor having a second gate and a second output connected to the first output; and

a current source connected to the first gate and the second gate and configured to generate the bias current.

14 . The system of claim 13 , wherein:

the rectification transistor comprises:

a first transistor; and

a second transistor connected in parallel with the first transistor, and

the diode connected compensation transistor comprises:

a third transistor; and

a fourth transistor connected in series with the third transistor.

15 . The system of claim 10 , wherein the envelope detector comprises:

a first capacitor connected in parallel with the first diode;

a current source configured to generate an integer multiple of the bias current connected in parallel with the first diode;

a third diode, wherein the third diode is threshold compensated by the bias current;

a second capacitor connected in parallel with the third diode; and

a voltage divider connected in parallel with the third diode.

16 . The system of claim 10 , wherein:

the second diode comprises an n-type diode,

the RF-DC converter comprises a p-type diode threshold compensated by the bias current and connected to the n-type diode,

a sampling capacitor is connected to a node between an input of the p-type diode and an output of the n-type diode; and

a load capacitor is connected to an output of the p-type diode.

17 . A method, comprising:

receiving a radio frequency (RF) input signal;

harvesting energy from the RF input signal to generate a supply voltage;

generating a bias current based on the supply voltage;

generating a signal corresponding to transitions in the RF input signal using a first diode

generating an interrupt signal responsive to detecting a wake-up pattern in the signal; and

compensating a threshold of the first diode using the bias current.

18 . The method of claim 17 , wherein harvesting energy from the RF input signal comprises:

compensating a threshold of an n-type diode using the bias current; and

compensating a threshold of a p-type diode using the bias current, wherein:

the n-type diode is connected to the p-type diode,

a sampling capacitor is connected to a node between an input of the p-type diode and an output of the n-type diode; and

a load capacitor is connected to an output of the p-type diode.

19 . The method of claim 17 , comprising:

detecting a pattern in the transitions in the RF input signal after the supply voltage exceeds a first voltage; and

storing at least some of the energy in an energy storage device responsive to the supply voltage exceeding a second voltage greater than the first voltage.

20 . The method of claim 17 , wherein generating the signal corresponding to transitions in the RF input signal comprises:

generating a first reference signal using the first diode, a first capacitor connected in parallel with the first diode, and a current source configured to generate an integer multiple of the bias current connected in parallel with the first diode; and

generating a second reference signal using a second diode threshold compensated by the bias current, a second capacitor connected in parallel with the second diode, and a voltage divider connected in parallel with the second diode.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Oct 21, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION; INFINEON TECHNOLOGIES AMERICAS CORP.
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073140/0554 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2023
From: SHETTY, DARSHAN BHASKAR; STEFFAN, CHRISTOPH; HOLWEG, GERALD
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 062675/0731 →
Continuity (2)
Provisional Application 63402454 · Aug 30, 2022
Related Publication 20240072578A1 · Feb 29, 2024
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