IP Library Granted Patent US 12,334,010
Granted Patent B2
US 12,334,010 · App. 18/122,401 · Granted Jun 17, 2025

Display device

Inventors: Donggyu Lee (Yongin-si, KR); Jae-Hyeon Jeon (Yongin-si, KR); Sehyuk Park (Yongin-si, KR); Jin-Wook Yang (Yongin-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
G09G3/3233G09G3/2096G09G2300/0819G09G2300/0852G09G2300/0861G09G2310/08G09G2320/0233G09G2320/0247G09G2320/0285
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Quick Facts
Patent No.
US 12,334,010
App. No.
18/122,401
Granted
Jun 17, 2025
Kind
B2
Abstract

A display device includes a light emitting element, a first transistor, and a second transistor connected between the first transistor and the light emitting element and including a gate electrode which receives an emission signal. One frame includes a first period a second period continuous with the first period. An emission off period of the emission signal has a first time duration during the first period, and the emission off period of the emission signal has a second time duration different from the first time duration during the second period.

Claims (52)

1. A display device comprising:

a light emitting element;

a first transistor;

a second transistor connected between the first transistor and the light emitting element and including a gate electrode which receives an emission signal; and

a driving controller which outputs an emission control signal in response to a first synchronization signal and a second synchronization signal,

wherein the emission control signal is output in response to an emission off control signal which is based on a compensation value corresponding to a count signal,

wherein one frame includes a first period and a second period continuous with the first period,

wherein the one frame includes a plurality of driving cycles, each of which includes an emission on period and an emission off period,

wherein the plurality of driving cycles includes a write cycle and a plurality of hold cycles,

wherein the driving controller includes a counter which resets in response to the first synchronization signal and counts up in response to the second synchronization signal, and outputs the count signal,

wherein the first synchronization signal indicates a start of the one frame, and the second synchronization signal indicates a start of each of the plurality of driving cycles, and

wherein an emission off period of the emission signal has a first time duration during the first period, and the emission off period of the emission signal has a second time duration different from the first time duration during the second period.

2. The display device of claim 1 , wherein the second transistor is turned off during the emission off period of the emission signal.

3. The display device of claim 1 , wherein the second time duration is shorter than the first time duration.

4. The display device of claim 1 , further comprising:

an emission driving circuit which outputs the emission signal in response to the emission control signal.

5. The display device of claim 4 , wherein the driving controller further includes:

a lookup table which stores the compensation value;

a selector which outputs the compensation value corresponding to the count signal as a deviation value;

an adder which adds an initial value and the deviation value and outputs emission off control signal; and

a control signal generator which outputs the emission control signal in response to the emission off control signal.

6. The display device of claim 5 , further comprising:

a memory which stores the initial value.

7. The display device of claim 1 , wherein the first period corresponds to a part of the plurality of driving cycles, and the second period corresponds to another part of the plurality of driving cycles.

8. The display device of claim 1 , wherein, when an operating frequency is a first frequency, the one frame includes the first period and the second period,

wherein, when the operating frequency is a second frequency lower than the first frequency, the one frame includes the first period, the second period, and a third period continuous with the second period, and

wherein the emission off period of the emission signal during the third period has a third time duration different from the first time duration and the second time duration.

9. A display device comprising:

a display panel including a pixel connected to a scan line, an emission control line, and a data line;

a scan driving circuit which outputs a scan signal to the scan line;

an emission driving circuit which outputs an emission signal to the emission control line; and

a driving controller which provides a scan control signal to the scan driving circuit and provides an emission control signal to the emission driving circuit,

wherein one frame includes a write cycle and a plurality of hold cycles,

wherein each of the write cycle and the plurality of hold cycles includes an emission on period and an emission off period,

wherein the driving controller includes an emission controller which outputs the emission control signal in response to a first synchronization signal and a second synchronization signal,

wherein the emission control signal is output in response to an emission off control signal which is based on a compensation value corresponding to a count signal,

wherein the emission controller includes a counter which resets in response to the first synchronization signal and counts up in response to the second synchronization signal and outputs the count signal,

wherein the first synchronization signal indicates a start of the one frame, and the second synchronization signal indicates a start of the write cycle and a start of each of the plurality of hold cycles, and

wherein the driving controller outputs the emission control signal in a way such that an emission off period of the emission signal has a first time duration during the write cycle and at least one hold cycle of the plurality of hold cycles and the emission off period of the emission signal has a second time duration different from the first time duration during remaining hold cycles of the plurality of hold cycles.

10. The display device of claim 9 , wherein the pixel includes:

a light emitting element;

a first transistor; and

a second transistor connected between the first transistor and the light emitting element and including a gate electrode which receives the emission signal.

11. The display device of claim 10 , wherein the second transistor is turned off by the emission signal during the emission off period of each of the write cycle and the plurality of hold cycles.

12. The display device of claim 10 , wherein, during each of the write cycle and the plurality of hold cycles, the second transistor is turned off by the emission signal and the second transistor is turned on by the emission signal.

13. The display device of claim 9 , wherein the second time duration is shorter than the first time duration.

14. The display device of claim 9 , wherein the emission controller further includes:

a lookup table which stores the compensation value;

a selector which outputs the compensation value corresponding to the count signal as a deviation value;

an adder which adds an initial value and the deviation value and outputs the emission off control signal; and

a control signal generator which outputs the emission control signal in response to the emission off control signal.

15. The display device of claim 14 , wherein the emission controller further includes a memory which stores the initial value.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2023
From: LEE, DONGGYU; JEON, JAE-HYEON; PARK, SEHYUK; YANG, JIN-WOOK
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 063958/0387 →
Priority Claims (1)
KR 10-2022-0070556 · Jun 10, 2022 · national
Continuity (1)
Related Publication 20230410741A1 · Dec 21, 2023
References Cited (24)
US 9542887B2 · Pyo · 2017 [cited by applicant]
US 10380943B2 · Choi et al. · 2019 [cited by applicant]
US 11043184B2 · An · 2021 [cited by examiner]
US 11138952B2 · Lee · 2021 [cited by examiner]
US 11302251B2 · Sung et al. · 2022 [cited by applicant]
US 11574574B2 · Kim · 2023 [cited by examiner]
US 11670212B2 · Lee · 2023 [cited by examiner]
US 11893954B2 · Kim · 2024 [cited by examiner]
US 11922866B1 · Sohn · 2024 [cited by examiner]
US 11948498B2 · Kim · 2024 [cited by examiner]
US 20050083280A1 · Hiraki · 2005 [cited by examiner]
US 20150371609A1 · Choi · 2015 [cited by examiner]
US 20170004766A1 · Cho · 2017 [cited by examiner]
US 20190014292A1 · Ishii · 2019 [cited by examiner]
US 20200066215A1 · Koo · 2020 [cited by examiner]
US 20200193915A1 · Noh · 2020 [cited by examiner]
US 20210398508A1 · Lee et al. · 2021 [cited by applicant]
US 20230306890A1 · Cho · 2023 [cited by examiner]
US 20230401997A1 · Jeon · 2023 [cited by examiner]
US 20240071273A1 · Bae · 2024 [cited by examiner]
KR 1020150114020A · 2015 [cited by applicant]
KR 1020190043653A · 2019 [cited by applicant]
KR 1020190063813A · 2019 [cited by applicant]
KR 102317876B1 · 2021 [cited by applicant]