IP Library Granted Patent US 12,126,703
Granted Patent B2
US 12,126,703 · App. 18/125,820 · Granted Oct 22, 2024

EtherCAT device with clock generation mode and clock propagation mode

Inventors: William Mahany (West Islip, NY); Ian Saturley (Warwickshire, GB); Lakshmi Narasimhan (Chennai, IN); Riyas Kattukandan (Kerala, IN); Ramya Kuppusamy (Karnataka, IN); Robert Zakowicz (Chandler, AZ)
Assignee: Microchip Technology Incorporated
H04L69/22G06F9/4418H04J3/0658H04L12/10
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Quick Facts
Patent No.
US 12,126,703
App. No.
18/125,820
Granted
Oct 22, 2024
Kind
B2
Abstract

An EtherCAT device with a node for use in an EtherCAT network is disclosed. The EtherCAT device includes: a clock circuit; a clock input to receive an input clock signal; a clock output to send an output clock signal; and control logic. The control logic is to determine whether to operate the EtherCAT device in a clock generation mode or a clock propagation mode, wherein in the clock generation mode, the clock circuit is to drive an oscillator to generate the input clock signal; and in the clock propagation mode, the clock circuit is to receive the input clock signal from another node in the EtherCAT network. The control logic is further to control the clock circuit to output the output clock signal for a subsequent node in the EtherCAT network based upon the input clock signal.

Claims (24)

1. An EtherCAT device for use as a node in an EtherCAT network, the EtherCAT device comprising:

a clock circuit;

a clock input to receive an input clock signal;

a clock output to send an output clock signal; and

control logic to:

determine whether to operate the EtherCAT device in a clock generation mode or a clock propagation mode, wherein:

in the clock generation mode, the clock circuit is to drive an oscillator to generate the input clock signal; and

in the clock propagation mode, the clock circuit is to receive the input clock signal from another node in the EtherCAT network, and

control the clock circuit to send the output clock signal at the clock output for a subsequent node in the EtherCAT network the output clock signal based upon the input clock signal.

2. The EtherCAT device of claim 1 , wherein the clock circuit includes at least one clock regeneration circuit to receive the input clock signal and generate the output clock signal from the input clock signal, the output clock signal to alternate between a first voltage level and a second voltage level supplied to the at least one clock regeneration circuit.

3. The EtherCAT device of claim 1 , wherein:

the clock circuit includes a first clock regeneration circuit to receive the input clock signal and generate a first output;

the clock circuit includes a second clock regeneration circuit to receive the input clock signal and generate a second output; and

the control logic is to output the output clock signal at the clock output based on the first output of the first clock regeneration circuit or the second output of the second clock regeneration circuit based upon whether the EtherCAT device is in the clock generation mode or clock propagation mode.

4. The EtherCAT device of claim 1 , wherein:

the clock circuit includes a crystal driver to, in the clock generation mode, provide a signal to the oscillator to drive the oscillator to generate the input clock signal; and

the clock circuit, in the clock generation mode, is to route the input clock signal to an input of the crystal driver.

5. A method, comprising:

receiving, through a clock input, an input clock signal;

sending, through a clock output, an output clock signal;

outputting the output clock signal for a subsequent node in an EtherCAT network based upon the input clock signal; and

determining whether to operate an EtherCAT device in the EtherCAT network in a clock generation mode or a clock propagation node, wherein:

in the clock generation mode, the method includes driving an oscillator to generate the input clock signal; and

in the clock propagation mode, the method includes receiving the input clock signal from another node in the EtherCAT network.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2023
From: MAHANY, WILLIAM; SATURLEY, IAN; NARASIMHAN, LAKSHMI; KATTUKANDAN, RIYAS; KUPPUSAMY, RAMYA; ZAKOWICZ, ROBERT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 063164/0751 →
Priority Claims (1)
IN 201911043952 · Oct 30, 2019 · national
Continuity (2)
Division 17030439 · Sep 24, 2020
Related Publication 20230231937A1 · Jul 20, 2023