Read/write control method and device for DDR dynamic random access memory, and system
View Patent ↗The disclosure provides a read/write control method and device for a DDR (Double Data Rate) dynamic random access memory, and a system. The device includes a read control signal generating unit and a read memory controller, and the read control signal generating unit is in signal connection with the read memory controller; the read control signal generating unit is configured for determining a minimum frame period from a plurality of received signal sources, generating a read control signal based on a delay time, and providing the read control signal to the read memory controller; and the read memory controller is configured for controlling the reading of video frames from the DDR dynamic random access memory according to the read control signal.
1. A read/write control device for a DDR dynamic random access memory, wherein the DDR dynamic random access memory is used for saving video frames of a plurality of received signal sources, the device comprises: a timing sequence detector, a read control signal generating unit and a read memory controller, the timing sequence detector is in signal connection with the read control signal generating unit, and the read control signal generating unit is in signal connection with the read memory controller;
the timing sequence detector is configured for: determining a plurality of frame periods respectively corresponding to the plurality of received signal sources based on respective time intervals between respective two adjacent vertical synchronization signals of the plurality of received signal sources; and determining vertical synchronization signals corresponding to each other of the plurality of received signal sources, and determining a plurality of frame period differences based on the vertical synchronization signals corresponding to each other of the plurality of received signal sources;
the read control signal generating unit is configured for: reading the plurality of frame periods and the plurality of frame period differences determined by the timing sequence detector; determining a minimum frame period from the plurality of frame periods; from the plurality of frame period differences, determining frame period differences of remaining signal sources with respect to a signal source having the minimum frame period; respectively summing the frame period differences of the respective remaining signal sources with the corresponding frame periods, to obtain a maximum value as a delay time; and delaying respective rising edges of the signal source having the minimum frame period, by the delay time, to generate a read control signal, and providing the read control signal to the read memory controller; and
the read memory controller is configured for: controlling reading of the video frames from the DDR dynamic random access memory according to the read control signal.
2. The device according to claim 1 , wherein the read control signal generating unit is further configured for:
delaying the respective rising edges of the signal source having the minimum frame period, by the delay time, to obtain a rising edge of the read control signal.
3. The device according to claim 2 , wherein the read memory controller is further configured for:
updating a read frame address to obtain an updated read frame address, under a condition that the rising edge of the read control signal arrives; and
according to the updated read frame address, reading the video frames from the DDR dynamic random access memory.
4. The device according to claim 3 , wherein the read memory controller is further configured for:
under a condition that the rising edge of the read control signal arrives and a difference between the frame period of one of the remaining signal sources and the minimum frame period is less than a preset value, the one of the remaining signal sources follows the signal source having the minimum frame period to synchronously update the read frame address; and
under a condition that the rising edge of the read control signal arrives and the difference between the frame period of the one of the remaining signal sources and the minimum frame period is not less than the preset value, the reading of the video frame of the one of the remaining signal sources is, repeatedly reading the video frame corresponding to a last write frame address corresponding to the one of the remaining signal sources.
5. The device according to claim 4 , wherein the preset value is: T_fast*0.1, wherein T_fast is the minimum frame period.
6. The device according to claim 4 , wherein the read frame address and write frame address of the signal source having the minimum frame period and the one of the remaining signal sources meet:
under the condition that the rising edge of the read control signal arrives and the difference between the frame period of the one of the remaining signal sources and the minimum frame period is less than the preset value, RDMA_fast_add=WDMA_fast_add−1, and RDMA_other_add=RDMA_fast_add; and
under the condition that the rising edge of the read control signal arrives and the difference between the frame period of the one of the remaining signal sources and the minimum frame period is not less than the preset value, RDMA_fast_add=WDMA_fast_add−1, and RDMA_other_add=WDMA_other_add−1,
wherein RDMA_fast_add is the read frame address of the signal source having the minimum frame period, WDMA_fast_add is the write frame address of the signal source having the minimum frame period, RDMA_other_add is the read frame address of the one of the remaining signal sources, and WDMA_other_add is the write frame address of the one of the remaining signal sources.
7. The device according to claim 1 , further comprising: a video data selection unit being in signal connection between write memory controllers and the DDR dynamic random access memory, and configured for selecting the plurality of received signal sources from input signal sources.
8. The device according to claim 1 , further comprising: an AXI bus controller configured for performing interrupt processing on an equipment interrupt request.
9. A read/write control method for a DDR dynamic random access memory, wherein the method is applied to the read/write control device for the DDR dynamic random access memory according to claim 1 , and the method comprises:
determining the plurality of frame periods respectively corresponding to the plurality of received signal sources based on the respective time intervals between respective two adjacent vertical synchronization signals of the plurality of received signal sources; and determining the vertical synchronization signals corresponding to each other of the plurality of received signal sources, and determining the plurality of frame period differences based on the vertical synchronization signals corresponding to each other of the plurality of received signal sources;
determining the minimum frame period from the plurality of frame periods; from the plurality of frame period differences, determining the frame period differences of the remaining signal sources with respect to the signal source having the minimum frame period; respectively summing the frame period differences of the respective remaining signal sources with the corresponding frame periods, to obtain the maximum value as the delay time; and delaying the respective rising edges of the signal source having the minimum frame period, by the delay time, to generate the read control signal; and
controlling the reading of the video frames from the DDR dynamic random access memory according to the read control signal.
10. The method according to claim 9 , wherein the step of generating the read control signal further comprises:
delaying the respective rising edges of the signal source having the minimum frame period, by the delay time, to obtain a rising edge of the read control signal.
11. The method according to claim 10 , further comprising:
updating a read frame address to obtain an updated read frame address under a condition that the rising edge of the read control signal arrives; and
according to the updated read frame address, reading the video frames from the DDR dynamic random access memory.
12. The method according to claim 11 , further comprising:
under a condition that the rising edge of the read control signal arrives and a difference between the frame period of one of the remaining signal sources and the minimum frame period is less than a preset value, the one of the remaining signal sources follows the signal source having the minimum frame period to synchronously update the read frame address; and
under a condition that the rising edge of the read control signal arrives and the difference between the frame period of the one of the remaining signal sources and the minimum frame period is not less than the preset value, the reading of the video frame of the one of the remaining signal sources is, repeatedly reading the video frame corresponding to a last write frame address corresponding to the one of the remaining signal sources.
13. The method according to claim 12 , wherein the preset value is: T_fast*0.1, wherein T_fast is the minimum frame period.
14. The method according to claim 12 , wherein the read frame address and write frame address of the signal source having the minimum frame period and the one of the remaining signal sources meet:
under the condition that the rising edge of the read control signal arrives and the difference between the frame period of the one of the remaining signal sources and the minimum frame period is less than the preset value, RDMA_fast_add=WDMA_fast_add−1, and RDMA_other_add=RDMA_fast_add; and
under the condition that the rising edge of the read control signal arrives and the difference between the frame period of the one of the remaining signal sources and the minimum frame period is not less than the preset value, RDMA_fast_add=WDMA_fast_add−1, and RDMA_other_add=WDMA_other_add−1,
wherein RDMA_fast_add is the read frame address of the signal source having the minimum frame period, WDMA_fast_add is the write frame address of the signal source having the minimum frame period, RDMA_other_add is the read frame address of the one of the remaining signal sources, and WDMA_other_add is the write frame address of the one of the remaining signal sources.
15. The method according to claim 9 , further comprising: selecting the plurality of received signal sources from input signal sources.
16. The method according to claim 9 , further comprising:
powering on the read/write control device for the DDR dynamic random access memory for initialization as a whole, wherein write frame address of the device is initialized to 3, and when the read memory controller is powered on, read frame address of the read memory controller is initialized to 0.
17. A monitor system, wherein the system comprises the read/write control device for the DDR dynamic random access memory according to claim 1 .
18. The system according to claim 17 , wherein the read/write control device for the DDR dynamic random access memory further comprises write memory controllers, and the write memory controllers are configured for controlling writing of the video frames of the plurality of received signal sources into the DDR dynamic random access memory.
19. The system according to claim 18 , wherein the read/write control device for the DDR dynamic random access memory further comprises an image superimposing unit, and the image superimposing unit is configured for superimposing the video frames read from the DDR dynamic random access memory and outputting the superimposed video frames.
20. The system according to claim 18 , wherein the read/write control device for the DDR dynamic random access memory further comprises a plurality of receivers corresponding to digital component serial interfaces and/or a plurality of receivers corresponding to high definition multimedia interfaces, the plurality of receivers corresponding to the digital component serial interfaces and/or the plurality of receivers corresponding to the high definition multimedia interfaces are in signal connection with a video data selection unit via the write memory controllers, and input ends of the video data selection unit are in one-to-one correspondence to the write memory controllers; and
the plurality of receivers corresponding to the digital component serial interfaces and/or the plurality of receivers corresponding to the high definition multimedia interfaces are configured for receiving monitor video data from the corresponding digital component serial interfaces and/or the corresponding high definition multimedia interfaces, and providing the monitor video data to the write memory controllers.