Method and system for fin-based voltage clamp
A method of clamping a voltage includes providing a fin-based field effect transistor (FinFET) device. The FinFET device includes an array of FinFETs. Each FinFET includes a source contact electrically coupled to a fin and a gate contact. The method also includes applying the voltage to the source contact and applying a second voltage to the gate contact. The voltage is greater than the second voltage. The method further includes increasing the voltage to a threshold voltage and conducting current from the source contact to the gate contact in response to the voltage reaching the threshold voltage.
1. An integrated electronic device comprising:
a first array of first FinFETs, each first FinFET comprising:
a central region characterized by a first electrical conductivity;
fin tips characterized by a second electrical conductivity less than the first electrical conductivity;
a first source contact; and
a common gate contact; and
a voltage clamp comprising:
a second array of second FinFETs, each second FinFET comprising:
a second source contact configured to receive a voltage; and
a second gate contact, wherein the voltage clamp is configured to conduct a current from the second source contact to the second gate contact in response to the voltage reaching a threshold voltage.
2. The integrated electronic device of claim 1 wherein the central region comprises a neutralized region including traps.
3. The integrated electronic device of claim 2 wherein the neutralized region comprises an ion implanted region.
4. The integrated electronic device of claim 2 wherein the first source contact is defined by a lateral source dimension and the neutralized region is defined by a lateral neutralized dimension greater than a depth of the neutralized region.
5. The integrated electronic device of claim 1 wherein each first FinFET further comprises a first central gate region disposed on a first lateral side of a fin and a second central gate region disposed on a second lateral side of the fin, wherein the first central gate region and the second central gate region are characterized by a third electrical conductivity.
6. The integrated electronic device of claim 1 wherein an area of each of the fin tips is between 1% and 10% of an area of fin.
7. The integrated electronic device of claim 1 wherein the fin tips have a tip length and a ratio of a fin length to the tip length is greater than 10:1.
8. The integrated electronic device of claim 7 wherein the ratio is greater than 25:1.
9. The integrated electronic device of claim 8 wherein the ratio is greater than 100:1.
10. The integrated electronic device of claim 1 wherein the voltage is ground.
11. The integrated electronic device of claim 1 wherein:
each second FinFET includes a gate region disposed between adjacent fins in the second array of second FinFETs; and
the second gate contact is electrically coupled to the gate region.
12. The integrated electronic device of claim 1 wherein the second source contact is an anode and the second gate contact is a cathode while conducting current from the second source contact to the second gate contact.
13. The integrated electronic device of claim 1 wherein the second FinFET comprises a III-N semiconductor.
14. The integrated electronic device of claim 13 wherein the III-N semiconductor comprises GaN.
15. An integrated electronic device comprising:
a voltage clamp comprising:
an array of FinFETs, each FinFET comprising:
a central region characterized by a first electrical conductivity;
fin tips characterized by a second electrical conductivity less than the first electrical conductivity;
a source contact configured to receive a voltage; and
a gate contact, wherein the voltage clamp is configured to conduct a current from the source contact to the gate contact in response to the voltage reaching a threshold voltage.
16. The integrated electronic device of claim 15 , wherein the central region comprises a neutralized region including traps.
17. The integrated electronic device of claim 15 , wherein:
each FinFET includes a gate region disposed between adjacent fins in the array of FinFETs; and
the gate contact is electrically coupled to the gate region.
18. A method of clamping a voltage, the method comprising:
providing a fin-based field effect transistor (FinFET) device, wherein the FinFET device includes an array of FinFETs, each FinFET comprising:
a central region characterized by a first electrical conductivity;
fin tips characterized by a second electrical conductivity less than the first electrical conductivity;
a source contact electrically coupled to a fin; and
a gate contact;
applying the voltage to the source contact;
applying a second voltage to the gate contact, wherein the voltage is greater than the second voltage;
increasing the voltage to a threshold voltage; and
conducting current from the source contact to the gate contact in response to the voltage reaching the threshold voltage.
19. The method of claim 18 , wherein the central region comprises a neutralized region including traps.
20. The method of claim 18 , wherein:
the FinFET device includes a gate region disposed between adjacent fins in the array of FinFETs; and
the gate contact is electrically coupled to the gate region.