Method and system for scanning MEMS cantilevers
A semiconductor substrate includes a first semiconductor layer, a first dielectric layer coupled to the first semiconductor layer, and a second semiconductor layer coupled to the first dielectric layer. The second semiconductor layer includes a base portion substantially aligned with the first dielectric layer and a cantilever portion protruding from an end of the first dielectric layer. The cantilever portion includes a tapered surface tapering from a bottom surface of the second semiconductor layer toward a top surface of the second semiconductor layer.
1. A semiconductor substrate, comprising:
a first semiconductor layer;
a first dielectric layer coupled to the first semiconductor layer; and
a second semiconductor layer coupled to the first dielectric layer, wherein the second semiconductor layer comprises:
a base portion substantially aligned with the first dielectric layer; and
a cantilever portion protruding from an end of the first dielectric layer, wherein the cantilever portion comprises a tapered surface tapering from a bottom surface of the second semiconductor layer toward a top surface of the second semiconductor layer.
2. The semiconductor substrate of claim 1 wherein the cantilever portion further comprises a first lateral tapered surface tapering from a first side of the second semiconductor layer toward a second side of the second semiconductor layer opposite the first side.
3. The semiconductor substrate of claim 2 wherein the cantilever portion further comprises a second lateral tapered surface tapering from the second side of the second semiconductor layer toward the first side of the second semiconductor layer.
4. The semiconductor substrate of claim 3 wherein the first lateral tapered surface, the second lateral tapered surface, the tapered surface, and the top surface of the second semiconductor layer define an end tip.
5. The semiconductor substrate of claim 3 wherein a tapering of the first lateral tapered surface is more rapid than a tapering of the second lateral tapered surface.
6. The semiconductor substrate of claim 3 wherein a tapering of the first lateral tapered surface is slower than a tapering of the second lateral tapered surface.
7. The semiconductor substrate of claim 3 wherein a tapering of the first lateral tapered surface is identical to a tapering of the second lateral tapered surface.
8. The semiconductor substrate of claim 1 wherein the first semiconductor layer is characterized by a (1 1 0) crystal orientation and the second semiconductor layer is characterized by a (1 1 1) crystal orientation.
9. The semiconductor substrate of claim 1 wherein the first dielectric layer comprises a buried oxide layer.
10. A semiconductor substrate comprising:
a first semiconductor layer;
a first dielectric layer coupled to the first semiconductor layer;
a second semiconductor layer coupled to the first dielectric layer, wherein the second semiconductor layer comprises:
a base portion substantially aligned with the first dielectric layer; and
a cantilever portion protruding from an end of the first dielectric layer, wherein the cantilever portion comprises a tapered surface tapering from a bottom surface of the second semiconductor layer toward a top surface of the second semiconductor layer;
a second dielectric layer coupled to the second semiconductor layer; and
a third semiconductor layer coupled to the second dielectric layer.
11. The semiconductor substrate of claim 10 wherein the cantilever portion further comprises a first lateral tapered surface tapering from a first side of the second semiconductor layer toward a second side of the second semiconductor layer opposite the first side.
12. The semiconductor substrate of claim 11 wherein the cantilever portion further comprises a second lateral tapered surface tapering from the second side of the second semiconductor layer toward the first side of the second semiconductor layer.
13. The semiconductor substrate of claim 12 wherein the third semiconductor layer comprises:
a third lateral tapered surface tapering along a tapering direction of the first lateral tapered surface; and
a fourth lateral tapered surface tapering along a tapering direction of the second lateral tapered surface.
14. The semiconductor substrate of claim 13 wherein a tapering of the third lateral tapered surface is more rapid than a tapering of the fourth lateral tapered surface.
15. The semiconductor substrate of claim 13 wherein a tapering of the third lateral tapered surface is slower than a tapering of the fourth lateral tapered surface.
16. The semiconductor substrate of claim 13 wherein a tapering of the third lateral tapered surface is identical to a tapering of the fourth lateral tapered surface.
17. The semiconductor substrate of claim 10 wherein the second dielectric layer comprises a buried oxide layer.