IP Library Granted Patent US 12,423,229
Granted Patent B2
US 12,423,229 · App. 18/139,236 · Granted Sep 23, 2025

Systems and methods for memory representation and tracking

Inventors: Ramzi Ammari (Santa Clara, CA); Mukesh Garg (Stanford, CA); Changho Choi (San Jose, CA)
Assignee: Samsung Electronics Co., Ltd.
G06F12/08
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Quick Facts
Patent No.
US 12,423,229
App. No.
18/139,236
Filed
Apr 25, 2023
Granted
Sep 23, 2025
Kind
B2
Art Unit
2139
USPC
711/154
Abstract

Systems and method for memory representation and tracking are disclosed. A storage system may identify a request to allocate memory in a first storage medium. In response to the request, the storage system may represent the memory via at least a first node of a first data structure. The first node may store first information for a first portion of the memory and a second portion of the memory. A criterion may be monitored for at least one of the first portion or the second portion. An order of the first node in the first data structure may be updated based on detecting the criterion.

Claims (46)

1. A storage system comprising:

a first storage medium;

a processor configured to communicate with the first storage medium; and

a memory coupled to the processor, the memory storing instructions that, when executed by the processor, cause the processor to:

identify a request to allocate memory in the first storage medium;

in response to the request, represent the memory via a first node of a first data structure and a second node of a second data structure, wherein the first node stores first information for a first portion of the memory and a second portion of the memory, and the second node stores second information for the first portion of the memory and the second portion of the memory;

monitor a criterion for at least one of the first portion or the second portion; and

update an order of the first node in the first data structure based on detecting the criterion, wherein the instructions that cause the processor to update the order include instructions that cause the processor to alter a position of the first node in the first data structure relative to a position of a third node in the first data structure.

2. The storage system of claim 1 , wherein the first portion includes a first page of memory, and the second portion includes a second page of memory.

3. The storage system of claim 1 , wherein the first portion of the memory is contiguous to the second portion of the memory, wherein the update of the order of the first node causes movement of the first portion of the memory and the second portion of the memory as a group.

4. The storage system of claim 1 , wherein the instructions that cause the processor to detect the criterion include instructions that cause the processor to detect access to the at least one of the first portion or the second portion of the memory.

5. The storage system of claim 1 , wherein the instructions that cause the processor to update the order of the first node include instructions that cause the processor to:

compute a percentage of detections of the criterion; and

determine a location of the first node in the first data structure based on the percentage.

6. The storage system of claim 1 , wherein the first data structure is associated with a first tier of a memory hierarchy, and the second data structure is associated with a second tier of the memory hierarchy.

7. The storage system of claim 6 , wherein the first information identifies whether the first portion of the memory and the second portion of the memory belong to the first tier, and the second information identifies whether the first portion of the memory and the second portion of the memory belong to the second tier.

8. The storage system of claim 7 , wherein the instructions further cause the processor to:

identify, based on the first information or the second information, an association of the first portion with the first tier;

determine a condition for changing the association for the first portion; and

modify the first information and the second information to change the association for the first portion to the second tier.

9. The storage system of claim 1 , wherein the first node includes a link to the second node, wherein an update to the first information causes an update to the second information.

10. The storage system of claim 1 , wherein the instructions further cause the processor to:

identify a first size for allocating the memory;

identify a second size of the at least the first portion or the second portion; and determine a number of portions represented by the first node based on the first size and the second size, wherein a size of the first information is equal to the number of portions.

11. A method comprising:

identifying a request to allocate memory in a first storage medium;

in response to the request, representing the memory via a first node of a first data structure and a second node of a second data structure, wherein the first node stores first information for a first portion of the memory and a second portion of the memory, and the second node stores second information for the first portion of the memory and the second portion of the memory

monitoring a criterion for at least one of the first portion or the second portion; and

updating an order of the first node in the first data structure based on detecting the criterion, wherein the updating of the order include altering a position of the first node in the first data structure relative to a position of a third node in the first data structure.

12. The method of claim 11 , wherein the first portion includes a first page of memory, and the second portion includes a second page of memory.

13. The method of claim 11 , wherein the first portion of the memory is contiguous to the second portion of the memory, wherein the updating the order of the first node causes movement of the first portion of the memory and the second portion of the memory as a group.

14. The method of claim 11 , wherein the detecting of the criterion further includes detecting access to the at least one of the first portion or the second portion of the memory.

15. The method of claim 11 , wherein the updating the order of the first node includes:

computing a percentage of detections of the criterion; and

determining a location of the first node in the first data structure based on the percentage.

16. The method of claim 11 , wherein the first data structure is associated with a first tier of a memory hierarchy, and the second data structure is associated with a second tier of the memory hierarchy.

17. The method of claim 16 , wherein the first information identifies whether the first portion of the memory and the second portion of the memory belong to the first tier, and the second information identifies whether the first portion of the memory and the second portion of the memory belong to the second tier.

18. The method of claim 17 further comprising:

identifying, based on the first information or the second information, an association of the first portion with the first tier;

determining a condition for changing the association for the first portion; and

modifying the first information and the second information to change the association for the first portion to the second tier.

19. The method of claim 11 , wherein the first node includes a link to the second node, wherein an update to the first information causes an update to the second information.

20. The method of claim 11 further comprising:

identifying a first size for allocating the memory;

identifying a second size of the at least the first portion or the second portion; and

determining a number of portions represented by the first node based on the first size and the second size, wherein a size of the first information is equal to the number of portions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2024
From: AMMARI, RAMZI; GARG, MUKESH; CHOI, CHANGHO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 066459/0126 →
Continuity (2)
Provisional Application 63452610 · Mar 16, 2023
Related Publication 20240311297A1 · Sep 19, 2024
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