Granted Patent B2

US 12,436,334 · App. 18/141,753 · Granted Oct 7, 2025

Inventors: Arpan Dasgupta (Beacon, NY); Zahidur Chowdhury (New Windsor, NY); Takako Hirokawa (Ballston Lake, NY); Vaishnavi Karra (Hopewell Junction, NY); Norman Robson (Fishkill, NY)

Assignee: GlobalFoundries U.S. Inc.

G02B6/12004G02B6/0016G02B6/136H04N5/33G02B2006/12121G02B2006/12147

Abstract

Claims (31)

1. A structure for a photonics chip, the structure comprising:

a semiconductor substrate;

a back-end-of-line stack on the semiconductor substrate, the back-end-of-line stack including a first dielectric layer, a first plurality of metal features in the first dielectric layer, a second dielectric layer on the first dielectric layer, and a second plurality of metal features in the second dielectric layer, the second plurality of metal features having a non-overlapping relationship with the first plurality of metal features;

an edge coupler adjacent to the first plurality of metal features and the second plurality of metal features; and

a light source configured to supply light to the edge coupler, the light source having a light output,

wherein the edge coupler is positioned between the light source and the first plurality of metal features, the second plurality of metal features are positioned between the edge coupler and the first plurality of metal features, the first plurality of metal features and the second plurality of metal features are configured to redirect a portion of the light from the light source out of the photonics chip for detection, and the first plurality of metal features and the second plurality of metal features are configured to redirect the portion of the light as a function of an alignment between the light output and the edge coupler.

2. The structure of claim 1 wherein the first dielectric layer is free of metal features in an exclusion area adjacent to the first plurality of metal features, and the second plurality of metal features overlap with the exclusion area.

3. The structure of claim 1 wherein the second dielectric layer is free of metal features in an exclusion area adjacent to the second plurality of metal features, and the exclusion area overlaps with the first plurality of metal features.

4. The structure of claim 1 wherein the first plurality of metal features are arranged in a first row, the second plurality of metal features are arranged in a second row, the second plurality of metal features in the second row have a non-overlapping relationship with the first plurality of metal features the first row, and the first plurality of metal features in the first row are arranged between the second plurality of metal features in the second row and the edge coupler.

5. The structure of claim 1 wherein the light source is an optical fiber.

6. The structure of claim 1 wherein the light source is a laser chip.

7. The structure of claim 1 wherein the semiconductor substrate includes a cavity, and the light source is positioned inside the cavity.

8. The structure of claim 1 wherein the first plurality of metal features and the second plurality of metal features are configured to redirect the portion of the light for detection of a vertical placement of the light output relative to the edge coupler.

9. The structure of claim 8 wherein the first plurality of metal features and the second plurality of metal features are placed in a staircase pattern.

10. The structure of claim 1 wherein the first plurality of metal features and the second plurality of metal features are configured to redirect the portion of the light for detection in multiple dimensions of placement of the light output relative to the edge coupler.

11. The structure of claim 10 wherein the first plurality of metal features and the second plurality of metal features are placed in a staggered pattern.

12. The structure of claim 1 wherein the first plurality of metal features and the second plurality of metal features comprise copper.

13. The structure of claim 1 wherein the first dielectric layer and the second dielectric layer comprise silicon dioxide.

14. The structure of claim 1 wherein the edge coupler comprises silicon.

15. The structure of claim 1 wherein the edge coupler includes a plurality of segments.

16. The structure of claim 1 wherein the edge coupler is connected to a photonic integrated circuit on the photonics chip.

17. The structure of claim 1 wherein the edge coupler comprises a waveguide core, the first dielectric layer is free of metal features in an exclusion area adjacent to the first plurality of metal features, and the first plurality of metal features are positioned along a length of the waveguide core between the edge coupler and the exclusion area.

18. The structure of claim 4 wherein the edge coupler comprises a waveguide core, the first row is aligned transverse to a length of the waveguide core, and the second row is aligned transverse to a length of the waveguide core.

19. The structure of claim 4 wherein the first row is offset from the second row.

20. A method of forming a photonics chip, the method comprising:

forming an edge coupler on a semiconductor substrate;

forming a first dielectric layer of a back-end-of-line stack on the semiconductor substrate;

forming a first plurality of metal features of the back-end-of-line stack in the first dielectric layer;

forming a second dielectric layer of the back-end-of-line stack on the first dielectric layer; and

forming a second plurality of metal features of the back-end-of-line stack in the second dielectric layer,

wherein the second plurality of metal features have a non-overlapping relationship with the first plurality of metal features, and the edge coupler is formed adjacent to the first plurality of metal features and the second plurality of metal features, a light source is configured to supply light to the edge coupler, the light source has a light output, the edge coupler is positioned between the light source and the first plurality of metal features, the second plurality of metal features are positioned between the edge coupler and the first plurality of metal features, the first plurality of metal features and the second plurality of metal features are configured to redirect a portion of the light from the light source out of the photonics chip for detection, and the first plurality of metal features and the second plurality of metal features are configured to redirect the portion of the light as a function of an alignment between the light output and the edge coupler.

Assignments (1)

Continuity (1)

References Cited (15)