IP Library Granted Patent US 12,419,116
Granted Patent B2
US 12,419,116 · App. 18/143,940 · Granted Sep 16, 2025

Solar cells having hybrid architectures including differentiated p-type and n-type regions

Inventor: David D. Smith (Campbell, CA)
Assignee: Maxeon Solar Pte. Ltd.
H10F10/14H10F71/1221H10F77/122H10F77/707
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Quick Facts
Patent No.
US 12,419,116
App. No.
18/143,940
Granted
Sep 16, 2025
Kind
B2
Abstract

A solar cell, and methods of fabricating said solar cell, are disclosed. The solar cell can include a substrate having a light-receiving surface and a back surface. The solar cell can include a first semiconductor region of a first conductivity type disposed on a first dielectric layer, wherein the first dielectric layer is disposed on the substrate. The solar cell can also include a second semiconductor region of a second, different, conductivity type disposed on a second dielectric layer, where a portion of the second thin dielectric layer is disposed between the first and second semiconductor regions. The solar cell can include a third dielectric layer disposed on the second semiconductor region. The solar cell can include a first conductive contact disposed over the first semiconductor region but not the third dielectric layer. The solar cell can include a second conductive contact disposed over the second semiconductor region, where the second conductive contact is disposed over the third dielectric layer and second semiconductor region. In an embodiment, the third dielectric layer can be a dopant layer.

Claims (16)

1. A method of fabricating a solar cell, the method comprising:

forming a first dielectric layer on a back side of a substrate;

forming a first semiconductor region on the first dielectric layer;

forming an insulating layer on the first semiconductor region, the insulating layer having a vertical thickness;

forming a second dielectric layer on portions of the first semiconductor region and on portions of the back side of the substrate;

forming a second semiconductor region on the second dielectric layer, wherein a portion of the second dielectric layer is between the first and second semiconductor regions;

forming a third dielectric layer on the second semiconductor region;

forming a first conductive contact over the first semiconductor region but not over the third dielectric layer, wherein the first conductive contact is through the insulating layer, wherein the first conductive contact is in direct contact with a top surface of the insulating layer, and wherein the first conductive contact has an upper wide portion and a lower narrow portion, the upper wide portion having a vertical thickness greater than a vertical thickness of the lower narrow portion, and the vertical thickness of the lower narrow portion of the first conductive contact has the same vertical thickness of the insulating layer; and

forming a second conductive contact over the third dielectric layer and second semiconductor region, wherein the second conductive contact is through the third dielectric layer, and wherein the second conductive contact is laterally retracted from the third dielectric layer.

2. The method of claim 1 , wherein the third dielectric layer comprises an insulator layer.

3. The method of claim 1 , wherein the third dielectric layer comprises a dielectric selected from the group consisting of silicon oxide, silicon oxynitride and silicon nitride.

4. The method of claim 1 , wherein a portion of the second semiconductor region and a portion of the third dielectric layer are between the first and second conductive contact structures.

5. The method of claim 1 , wherein a portion of the second semiconductor region and a portion of the third dielectric layer are over the first semiconductor region.

6. The method of claim 1 , wherein the first and second conductive contacts each comprises a metal foil or a wire.

7. The method of claim 1 , wherein the second conductive contact is over the first and second semiconductor regions.

8. The method of claim 1 , wherein the first and second semiconductor regions comprise a first and second polycrystalline silicon emitter regions.

Assignments (5)
SECURITY INTEREST Recorded Jun 27, 2024
From: MAXEON SOLAR PTE. LTD.
To: DB TRUSTEES (HONG KONG) LIMITED
Reel/Frame 067924/0062 →
SECOND LIEN SECURITY INTEREST AGREEMENT Recorded Jun 26, 2024
From: MAXEON SOLAR PTE. LTD
To: DB TRUSTEES (HONG KONG) LIMITED
Reel/Frame 071343/0553 →
SECURITY INTEREST Recorded Jun 5, 2024
From: MAXEON SOLAR PTE. LTD.
To: DB TRUSTEES (HONG KONG) LIMITED
Reel/Frame 067637/0598 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2023
From: SUNPOWER CORPORATION
To: MAXEON SOLAR PTE. LTD.
Reel/Frame 063599/0854 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2023
From: SMITH, DAVID D.
To: SUNPOWER CORPORATION
Reel/Frame 063569/0616 →
Continuity (3)
Division 16586509 · Sep 27, 2019
Provisional Application 62739077 · Sep 28, 2018
Related Publication 20230275175A1 · Aug 31, 2023
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