METHOD AND SYSTEM FOR ERROR CHECKING IN WIRELESS COMMUNICATIONS

1 . A method for error checking in a wireless communication, the method comprising:

receiving a payload;

determining a final decoding result of the payload, wherein the final decoding result indicates a start state and an end state;

determining whether the end state is identical to the start state based on a state circularity check; and

determining to discard the final decoding result based on whether the end state is identical to the start state.

2 . The method of claim 1 , wherein determining the final decoding result further comprises:

decoding the payload according to Viterbi decoding techniques.

3 . The method of claim 1 , further comprising:

determining, according to the state circularity check, that the end state is not identical to the start state; and

discarding the final decoding result.

4 . The method of claim 1 , further comprising:

determining, according to the state circularity check, that the end state is identical to the start state; and

performing one or more error checks of the final decoding result.

5 . The method of claim 4 , wherein the payload includes one or more cyclic redundancy check (CRC) bits, and wherein the error check is a CRC.

6 . The method of claim 5 , further comprising:

determining, based on the CRC, that the end state is not identical to the start state; and

discarding the final decoding result.

7 . The method of claim 4 , wherein the error check is a path metric check.

8 . The method of claim 7 , further comprising:

determining, based on the path metric check, that a maximum state metric is smaller than a threshold value, wherein the maximum state metric is indicative of a number of states included in the final decoding result; and

discarding the final decoding result.

9 . The method of claim 4 , wherein the error check is a payload field validness check.

10 . The method of claim 9 , further comprising:

determining, based on the payload field validness check, that the payload includes an invalid field combination; and

discarding the final decoding result.

11 . The method of claim 1 , further comprising:

decoding the payload according to any of maximum a posteriori (MAP) techniques, logarithmic maximum a posteriori (LOG-MAP) techniques, maximum logarithmic maximum a posteriori (MAX-LOG-MAP) techniques, and/or soft output Viterbi algorithms (SOVA).

12 . The method of claim 1 , wherein the payload is received on any tail-biting coded channels.

13 . A method comprising:

receiving a payload;

determining a final decoding result of the payload, wherein the final decoding result indicates a start state and an end state, and wherein determining the final decoding result further comprising: decoding the payload;

determining whether the end state is identical to the start state based on a state circularity check;

performing an error check of the final decoding result; and

determining to discard the final decoding result based on (1) whether the end state is identical to the start state or (2) the error check.

14 . The method of claim 13 , wherein decoding the payload comprises: decoding the payload according to Viterbi decoding techniques.

15 . The method of claim 13 , wherein the error check is any of a cyclic redundancy check (CRC), a path metric check, and/or a payload field validness check.

16 . The method of claim 13 , further comprising:

determining that the end state is not identical to the start state; and

discarding the final decoding result.

17 . The method of claim 13 , further comprising:

determining that the end state is identical to the start state; and

discarding the final decoding result based on the error check.

18 . The method of claim 13 , wherein performing the error check further comprises:

upon determining that the end state is identical to the start state, determining to perform the error check.

19 . The method of claim 13 , wherein the payload is received on a physical downlink control channel (PDCCH).

20 . A system comprising:

a receiver operable to receive a payload;

a processor configured to:

determine a final decoding result of the payload, wherein the final decoding result indicates a start state and an end state;

determine whether the end state is identical to the start state based on a state circularity check; and

determine to discard the final decoding result based on whether the end state is identical to the start state.