IP Library Granted Patent US 12,185,502
Granted Patent B2
US 12,185,502 · App. 18/147,479 · Granted Dec 31, 2024

Semiconductor apparatus and electronic apparatus

Inventors: Shinya Sasaki (Ebina, JP); Yoshihiro Nakata (Atsugi, JP)
Assignee: FUJITSU LIMITED
H05K7/2039H01L23/345H01L23/4006H01L24/10H01L2224/161
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Quick Facts
Patent No.
US 12,185,502
App. No.
18/147,479
Granted
Dec 31, 2024
Kind
B2
Abstract

A semiconductor apparatus includes a substrate, a plurality of heat generating elements mounted on the substrate, a heat dissipation member fixed to the substrate and disposed such that the heat generating elements are interposed between the heat dissipation member and the substrate, at least one first heat conduction member provided on a first surface of the heat dissipation member, the first surface facing the heat generating elements, and a plurality of second heat conduction members each provided on a second surface of a corresponding one of the heat generating elements, the second surface facing the heat dissipation member, wherein the at least one first heat conduction member and the second heat conduction members are in contact with each other at an interface between opposing surfaces thereof.

Claims (17)

1. A semiconductor apparatus comprising:

a substrate;

a plurality of heat generating elements mounted on the substrate;

a heat dissipation member fixed to the substrate and disposed such that the heat generating elements are interposed between the heat dissipation member and the substrate;

at least one first heat conduction member provided on a first surface of the heat dissipation member, the first surface facing the heat generating elements; and

a plurality of second heat conduction members each provided on a second surface of a corresponding one of the heat generating elements, the second surface facing the heat dissipation member,

wherein the at least one first heat conduction member and the second heat conduction members are in contact with each other at an interface between opposing surfaces thereof,

wherein in a direction perpendicular to a surface of the substrate on which the heat generating elements are mounted, a thermal expansion coefficient of the second heat conduction members is greater than a thermal expansion coefficient of the at least one first heat conduction member, and

wherein the heat generating elements each include a fan-out wafer level package.

2. The semiconductor apparatus as claimed in claim 1 , wherein the at least one first heat conduction member and the second heat conduction members are solid.

3. The semiconductor apparatus as claimed in claim 1 , wherein the at least one first heat conduction member contains a resin having a glass transition point of 30° C. or lower.

4. The semiconductor apparatus as claimed in claim 1 , wherein the second heat conduction members contain a resin having a glass transition point of 30° C. or lower.

5. The semiconductor apparatus as claimed in claim 1 , wherein the heat generating elements each include a semiconductor chip that is in direct contact with a corresponding one of the second heat conduction members.

6. The semiconductor apparatus as claimed in claim 1 , further comprising a fixing member configured to fix the heat dissipation member to the substrate.

7. The semiconductor apparatus as claimed in claim 1 , wherein the at least one first heat conduction member has a thermal expansion coefficient of 80 ppm/K or more in a direction perpendicular to a surface of the substrate on which the heat generating elements are mounted.

8. The semiconductor apparatus as claimed in claim 1 , wherein the second heat conduction members each has a thermal expansion coefficient of 80 ppm/K or more in a direction perpendicular to a surface of the substrate on which the heat generating elements are mounted.

9. An electronic apparatus comprising the semiconductor apparatus of claim 1 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 5, 2026
From: FUJITSU LIMITED
To: 1FINITY INC.
Reel/Frame 074197/0244 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2022
From: SASAKI, SHINYA; NAKATA, YOSHIHIRO
To: FUJITSU LIMITED
Reel/Frame 062237/0625 →
Priority Claims (1)
JP 2022-052036 · Mar 28, 2022 · national
Continuity (1)
Related Publication 20230309267A1 · Sep 28, 2023