IP Library Granted Patent US 12,057,383
Granted Patent B2
US 12,057,383 · App. 18/148,001 · Granted Aug 6, 2024

Bonded structures with integrated passive component

Inventors: Belgacem Haba (Saratoga, CA); Ilyas Mohammed (Santa Clara, CA); Rajesh Katkar (Milpitas, CA); Gabriel Z. Guevara (San Jose, CA); Javier A. DeLaCruz (San Jose, CA); Shaowu Huang (Sunnyvale, CA); Laura Willis Mirkarimi (Sunol, CA)
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
H01L23/49838H01G2/02H01G4/1245H01G4/228H01G4/30H01G4/40H01L23/48H01L23/49822H01L23/49827H01L23/5223H01L24/08H01L24/32H05K1/18H01G4/38H01L23/49816H01L23/66H01L24/05H01L24/80H01L2223/6666H01L2223/6672H01L2224/03845H01L2224/05005H01L2224/05017H01L2224/05556H01L2224/05567H01L2224/05576H01L2224/05647H01L2224/05686H01L2224/0807H01L2224/08265H01L2224/16265H01L2224/32265H01L2224/80203H01L2224/80895H01L2224/80896H01L2224/80948H01L2924/19011H01L2924/19041H01L2924/19103H05K1/0231H05K1/185H05K2201/10015
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,057,383
App. No.
18/148,001
Granted
Aug 6, 2024
Kind
B2
Abstract

In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.

Claims (39)

1. A bonded structure comprising:

an integrated device die comprising a first surface comprising a first non-conductive region and a first plurality of conductive regions; and

a passive electronic component comprising:

a second surface directly hybrid bonded to the first surface, such that a second non-conductive region of the second surface is directly bonded to the first non-conductive region without an intervening adhesive and a second plurality of conductive regions is directly bonded to the first plurality of conductive regions without an intervening adhesive; and

a plurality of capacitors electrically connected to at least some of the second plurality of conductive regions, wherein the capacitors of the passive electronic component form part of a power delivery network for the integrated device die.

2. The bonded structure of claim 1 , wherein the plurality of capacitors of the passive electronic component improve the stability of the power supply to the integrated device die.

3. The bonded structure of claim 1 , wherein the passive electronic component reduces impedance at frequencies above 500 MHz, as compared to a configuration in which the integrated device die and the passive electronic component are not directly bonded.

4. The bonded structure of claim 1 , wherein the plurality of capacitors of the passive electronic component are not separated from the integrated device die by any standoff.

5. The bonded structure of claim 1 , further comprising a redistribution layer between the plurality of capacitors and the second plurality of conductive regions.

6. The bonded structure of claim 1 , wherein the plurality of capacitors have electrode surfaces that are generally perpendicular to the second surface.

7. The bonded structure of claim 1 , wherein the second surface of the passive electronic component covers the entirety of the first surface of the integrated device die.

8. The bonded structure of claim 1 , wherein the hybrid bonded integrated device die and passive electronic component are both singulated from a wafer-to-wafer bond.

9. The bonded structure of claim 1 , wherein sidewalls of the integrated device die and passive electronic component are aligned in a manner characteristic of singulation after bonding.

10. The bonded structure of claim 1 , wherein the passive electronic component comprises materials having a dielectric constant greater than 5.

11. The bonded structure of claim 10 , wherein the passive electronic component comprises materials having a dielectric constant greater than 20.

12. The bonded structure of claim 1 , wherein the passive electronic component includes an array of capacitive cells having an effective capacitance per unit area of at least 5 nF/mm 2 .

13. The bonded structure of claim 12 , wherein the effective capacitance per unit area is at least 50 nF/mm 2 .

14. The bonded structure of claim 12 , wherein the effective capacitance per unit area is at least 100 nF/mm 2 .

15. The bonded structure of claim 12 , wherein the effective capacitance per unit area is at least 200 nF/mm 2 .

16. The bonded structure of claim 1 , wherein the passive electronic component further includes vias providing signals separate from the power delivery network to the integrated device die.

17. The bonded structure of claim 1 , wherein the integrated device die comprises a processor.

18. The bonded structure of claim 1 , wherein the integrated device die further comprises a substrate and a plurality of active devices on the same side of the substrate as the first surface.

19. A bonded structure comprising:

an integrated device die comprising a first surface comprising a first non-conductive region and a first plurality of conductive regions; and

an electronic component comprising:

a second surface directly hybrid bonded to the first surface, such that a second non-conductive region of the second surface is directly bonded to the first non-conductive region without an intervening adhesive and a second plurality of conductive regions is directly bonded to the first plurality of conductive regions without an intervening adhesive; and

a plurality of capacitors electrically connected to at least some of second plurality of conductive regions, wherein the capacitors filter a component of a power signal delivered to the integrated device die.

20. The bonded structure of claim 19 , wherein the plurality of capacitors cover at least 55% of an active surface of the integrated device die.

21. The bonded structure of claim 20 , wherein the plurality of capacitors cover at least 75% of an active surface of the integrated device die.

22. The bonded structure of claim 19 , wherein the plurality of capacitors filter out DC components of signals provided to the integrated device die.

23. The bonded structure of claim 19 , wherein the plurality of capacitors are deep trench capacitors.

24. The bonded structure of claim 19 , wherein the electronic component comprises materials having a dielectric constant greater than 5.

25. The bonded structure of claim 24 , wherein the materials have a dielectric constant greater than 20.

26. The bonded structure of claim 25 , wherein the materials have a dielectric constant greater than 100.

27. The bonded structure of claim 19 , wherein the electronic component further comprises vias to allow electrical communication through the electronic component.

28. The bonded structure of claim 27 , wherein the vias provide signals to the integrated device die separate from the power signal.

29. The bonded structure of claim 19 , wherein the first surface is on a front side of the integrated device die.

30. The bonded structure of claim 19 , wherein the first surface is on a back side of the integrated device die.

31. The bonded structure of claim 30 , wherein the integrated device die comprises one or more vias electrically connecting at least one of the first plurality of conductive regions to a device on a front side of the integrated device die.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2024
From: HABA, BELGACEM; MOHAMMED, LLYAS; KATKAR, RAJESH; GUEVARA, GABRIEL Z.; DELACRUZ, JAVIER A.; HUANG, SHAOWU; MIRKARIMI, LAURA WILLS
To: INVENSAS BONDING TECHNOLOGIES, INC.
Reel/Frame 067757/0227 →
CHANGE OF NAME Recorded Jun 18, 2024
From: INVENSAS BONDING TECHNOLOGIES, INC.
To: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Reel/Frame 067776/0333 →
SECURITY INTEREST Recorded May 3, 2023
From: ADEIA GUIDES INC.; ADEIA IMAGING LLC; ADEIA MEDIA HOLDINGS LLC; ADEIA MEDIA SOLUTIONS INC.; ADEIA SEMICONDUCTOR ADVANCED TECHNOLOGIES INC.; ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.; ADEIA SEMICONDUCTOR INC.; ADEIA SEMICONDUCTOR SOLUTIONS LLC; ADEIA SEMICONDUCTOR TECHNOLOGIES LLC; ADEIA SOLUTIONS LLC
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 063529/0272 →
Continuity (4)
Continuation 15856391 · Dec 28, 2017
Provisional Application 62518472 · Jun 12, 2017
Provisional Application 62440161 · Dec 29, 2016
Related Publication 20230317591A1 · Oct 5, 2023
Cited By (2)
US 12,400,926 US 12,710,588