Gate formation on a quantum processor
In a general aspect, a gate is formed for a quantum processor. In some implementations, an arbitrary program is received. The arbitrary program includes a first sequence of quantum logic gates, which includes a parametric XY gate. A native gate set is identified, which includes a set of quantum logic gates associated with a quantum processing unit. A second sequence of quantum logic gates corresponding to the parametric XY gate is identified, which includes a parametric quantum logic gate. Each of the quantum logic gates in the second sequence is selected from the native gate set. A native program is generated. The native program includes a third sequence of quantum logic gates. The third sequence of quantum logic gates corresponds to the first sequence of quantum logic gates and includes the second sequence of quantum logic gates. The native program is provided for execution by the quantum processing unit.
1. A method comprising:
identifying a sequence of quantum logic gates associated with a quantum processor unit, the sequence corresponding to a parametric multi-qubit quantum logic gate for application to a plurality of qubits, the sequence comprising a plurality of flux pulses; and
configuring frame tracking for the sequence of quantum logic gates, wherein configuring the frame tracking comprises determining shifts on relative frames of the plurality of qubits during the sequence.
2. The method of claim 1 , wherein configuring the frame tracking comprises determining relative phases of respective pairs of flux pulses.
3. The method of claim 1 , wherein configuring the frame tracking is performed by a compiler.
4. The method of claim 1 , comprising:
updating an entangled phase of at least one flux pulse of the plurality of flux pulses according to the shifts on relative frames.
5. The method of claim 1 , wherein the sequence further comprises two or more parametric single-qubit rotation gates.
6. The method of claim 5 , wherein configuring the frame tracking comprises:
determining first relative phases between flux pulses in the respective pairs of flux pulses; and
determining second relative phases of each flux pulse in the respective pairs of flux pulses and each of the two or more parametric single-qubit rotation gates.
7. The method of claim 5 , wherein the relative frames comprise single qubit frames associated with the two or more parametric single-qubit rotation gates and multi-qubit frames associated with the plurality of flux pulses, and determining shifts on relative frames of the plurality of qubits comprises:
determining relative phases between each single-qubit frame and each multi-qubit frame.
8. The method of claim 1 , wherein the parametric multi-qubit quantum logic gate comprises a parametric XY gate; the sequence comprises a first flux pulse, a second flux pulse, and parametric single-qubit rotation gates, and configuring the frame tracking comprises:
calibrating the first and second flux pulses;
determining first relative phases between the first and second flux pulses; and
determining second relative phases between each of the first and second flux pulses and each of the parametric single-qubit rotation gates.
9. The method of claim 8 , wherein calibrating the first flux pulse comprises:
applying the first flux pulse to a tunable-frequency qubit device in the quantum processor unit; and
determining a resonance condition by sweeping at least one of frequency, amplitude, or duration of the first flux pulse applied on the tunable-frequency qubit device.
10. The method of claim 8 , wherein each of the first and second flux pulses comprises a √{square root over (iSWAP)} gate.
11. The method of claim 10 , wherein the √{square root over (iSWAP)} gate is applied on a pair of qubits defined by a tunable-frequency qubit device and a fixed-frequency qubit device in the quantum processor unit.
12. The method of claim 8 , wherein the first flux pulse comprises a first √{square root over (iSWAP)} gate, the second flux pulse comprises a second √{square root over (iSWAP)} gate, and determining the first relative phases of the first and second flux pulses comprises:
calibrating the first and second √{square root over (iSWAP)} gates;
determining first relative phases between the first and second √{square root over (iSWAP)} gates; and
determining second relative phases between each of the first and second √{square root over (iSWAP)} gates and each of the parametric single-qubit rotation gates.
13. The method of claim 12 , wherein calibrating the first √{square root over (iSWAP)} gate comprises:
applying the first flux pulse to a tunable-frequency qubit device; and
determining a resonance condition by sweeping at least one of frequency, amplitude or duration of the first flux pulse applied on the tunable-frequency qubit device.
14. The method of claim 8 , wherein identifying the sequence comprises:
determining a value of a variable parameter specified by the parametric XY gate; and
assigning the value to a variable parameter of one or more quantum logic gates in the sequence.
15. The method of claim 1 , wherein the quantum processor unit comprises a superconducting quantum processor circuit comprising a plurality of qubit devices.
16. The method of claim 1 , wherein the sequence further comprises a non-parametric quantum logic gate.
17. The method of claim 1 , wherein the sequence comprises a plurality of parametric two-qubit quantum logic gates.
18. A computing system comprising:
a quantum processor unit; and
one or more computing devices configured to:
identify a sequence of quantum logic gates associated with the quantum processor unit, the sequence corresponding to a parametric multi-qubit quantum logic gate for application to a plurality of qubits, the sequence comprising a plurality of flux pulses; and
configure frame tracking for the sequence, wherein configuring the frame tracking comprises determining shifts on relative frames of the plurality of qubits during the sequence.
19. The computing system of claim 18 , wherein the one or more computing devices are configured to:
configure the frame tracking by determining relative phases of respective pairs of flux pulses.
20. The computing system of claim 18 , wherein the sequence further comprises two or more parametric single-qubit rotation gates.
21. The computing system of claim 20 , wherein the one or more computing devices are configured to configure the frame tracking by:
determining first relative phases between flux pulses in the respective pairs of flux pulses; and
determining second relative phases of each flux pulse in the respective pairs of flux pulses and each of the two or more parametric single-qubit rotation gates.
22. The computing system of claim 20 , wherein the relative frames comprise single qubit frames associated with the two or more parametric single-qubit rotation gates and multi-qubit frames associated with the plurality of flux pulses, and the one or more computing devices are configured to determine shifts on relative frames of the plurality of qubits by determining relative phases between each single-qubit frame and each multi-qubit frame.
23. The computing system of claim 18 , wherein the one or more computing devices comprise a compiler configured to configure the frame tracking.
24. The computing system of claim 18 , wherein the one or more computing devices are configured to:
update an entangled phase of at least one flux pulse of the plurality of flux pulses according to the shifts on relative frames.
25. The computing system of claim 18 , wherein the parametric multi-qubit quantum logic gate comprises a parametric XY gate; the sequence comprises a first flux pulse, a second flux pulse, and parametric single-qubit rotation gates, and the one or more computing devices are configured to configure the frame tracking by
calibrating the first and second flux pulses;
determining first relative phases between the first and second flux pulses; and
determining second relative phases between each of the first and second flux pulses and each of the parametric single-qubit rotation gates.
26. The computing system of claim 25 , wherein the one or more computing devices are configured to calibrate the first flux pulse by:
applying the first flux pulse to a tunable-frequency qubit device in a quantum processor unit; and
determining a resonance condition by sweeping at least one of frequency, amplitude, or duration of the first flux pulse applied on the tunable-frequency qubit device.
27. The computing system of claim 25 , wherein each of the first and second flux pulses comprises a √{square root over (iSWAP)} gate.
28. The computing system of claim 27 , wherein the √{square root over (iSWAP)} gate is applied on a pair of qubits defined by a tunable-frequency qubit device and a fixed-frequency qubit device in the quantum processor unit.
29. The computing system of claim 25 , wherein the first flux pulse comprises a first √{square root over (iSWAP)} gate, the second flux pulse comprises a second √{square root over (iSWAP)} gate, and the one or more computing devices are configured to determine the first relative phases of the first and second flux pulses by:
calibrating the first and second √{square root over (iSWAP)} gates;
determining first relative phases between the first and second √{square root over (iSWAP)} gates; and
determining second relative phases between each of the first and second √{square root over (iSWAP)} gates and each of the parametric single-qubit rotation gates.
30. The computing system of claim 29 , wherein the one or more computing devices are configured to calibrate the first √{square root over (iSWAP)} gate by:
applying the first flux pulse to the tunable-frequency qubit device; and
determining a resonance condition by sweeping at least one of frequency, amplitude or duration of the first flux pulse applied on the tunable-frequency qubit device.
31. The computing system of claim 25 , wherein the one or more computing devices are configured to identify the sequence by:
determining a value of a variable parameter specified by the parametric XY gate; and
assigning the value to a variable parameter of one or more quantum logic gates in the sequence.
32. The computing system of claim 18 , wherein the quantum processor unit comprises a superconducting quantum processor circuit comprising a plurality of qubit devices.
33. The computing system of claim 18 , wherein the sequence further comprises a non-parametric quantum logic gate.