MICRO-LED, MICRO-LED ARRAY PANEL AND MANUFACTURING METHOD THEREOF

1 . A micro-LED, comprising:

a first type semiconductor layer;

a first type cap layer formed on the first type semiconductor layer; and

a light emitting layer formed on the first type cap layer; wherein

the first type semiconductor layer comprises a mesa structure, a trench, and an ion implantation fence separated from the mesa structure; the ion implantation fence is formed around the trench and the trench is formed around the mesa structure, wherein an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure.

2 . The micro-LED according to claim 1 , wherein a top surface of the ion implantation fence is not higher than a top surface of the first type semiconductor layer.

3 . The micro-LED according to claim 1 , wherein a bottom surface of the ion implantation fence is aligned with or higher than a bottom surface of the first type semiconductor layer.

4 . The micro-LED according to claim 1 , wherein the trench extends up through a top surface of the first type semiconductor layer to a bottom surface of the first type cap layer.

5 . The micro-LED according to claim 4 , wherein a top surface of the ion implantation fence is not higher than a top surface of the trench.

6 . The micro-LED according to claim 1 , wherein the trench does not extend up through a top surface of the first type semiconductor layer.

7 . The micro-LED according to claim 6 , wherein a top surface of the ion implantation fence is not lower than a top surface of the trench.

8 . The micro-LED according to claim 6 , wherein a top surface of the ion implantation fence is lower than a top surface of the trench.

9 . The micro-LED according to claim 1 , further comprising:

a second type cap layer formed on the light emitting layer; and

a second type semiconductor layer formed on the second type cap layer;

wherein a conductive type of the second type semiconductor layer is different from the conductive type of the first type semiconductor layer.

10 . The micro-LED according to claim 9 , wherein the mesa structure, the trench, and the ion implantation fence are a first mesa structure, a first trench, and a first ion implantation fence, respectively; wherein the second type semiconductor layer comprises a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure; wherein a bottom surface of the second ion implantation fence is not lower than a bottom surface of the second type semiconductor layer; and

the second ion implantation fence is formed around the second trench and the second trench is formed around the second mesa structure; wherein an electrical resistance of the second ion implantation fence is higher than an electrical resistance of the second mesa structure.

11 . The micro-LED according to claim 10 , wherein the second trench extends down through the bottom surface of the second type semiconductor layer to a top surface of the second type cap layer.

12 . The micro-LED according to claim 11 , wherein the bottom surface of the second ion implantation fence is higher than or aligned with a bottom surface of the second trench.

13 . The micro-LED according to claim 10 , wherein the second trench does not extend down through the bottom surface of the second type semiconductor layer.

14 . The micro-LED according to claim 13 , wherein the bottom surface of the second ion implantation fence is lower than or aligned with a bottom surface of the second trench.

15 . The micro-LED according to claim 13 , wherein the bottom surface of the second ion implantation fence is higher than a bottom surface of the second trench.

16 . The micro-LED according to claim 10 , wherein a top surface of the second ion implantation fence is aligned with or lower than a top surface of the second type semiconductor layer; or the top surface of the second ion implantation fence is higher than the top surface of the second type semiconductor layer.

17 . The micro-LED according to claim 10 , wherein the first mesa structure comprises one or more stair structures; and the second mesa structure comprises one or more stair structures.

18 . The micro-LED according to claim 10 , wherein a width of the first trench is not greater than 50% of a diameter of the first mesa structure; and a width of the second trench is not greater than 50% of a diameter of the second mesa structure.

19 . The micro-LED according to claim 18 , wherein the width of the first trench is not greater than 200 nm; and the width of the second trench is not greater than 200 nm.

20 . The micro-LED according to claim 10 , wherein the first ion implantation fence comprises a first light absorption material, the second ion implantation fence comprises a second light absorption material; wherein a conductive type of the first light absorption material is the same as the conductive type of the first type semiconductor, a conductive type of the second light absorption material is the same as the conductive type of the second type semiconductor, and the first light absorption material and the second light absorption material are selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, AlGaN.

21 . The micro-LED according to claim 9 , wherein a thickness of the first type semiconductor layer is greater than a thickness of the second type semiconductor layer.

22 . The micro-LED according to claim 1 , further comprising a bottom isolation layer filled in the trench.

23 . The micro-LED according to claim 22 , wherein a material of the bottom isolation layer is selected from one or more of SiO 2 , SiN x , Al 2 O 3 , AlN, HfO 2 , TiO 2 , or ZrO 2 .

24 . The micro-LED according to claim 9 , further comprising a top contact and a top conductive layer, wherein the top contact and the top conductive layer are formed on a top surface of the second type semiconductor layer.

25 . The micro-LED according to claim 10 , further comprising a top conductive layer and a top contact; wherein the top contact is formed on a top surface of the second mesa structure; and the top conductive layer is formed on a top surface and sidewalls of the second mesa structure, on a top surface and sidewalls of the second ion implantation fence and fills in the second trench.

26 . The micro-LED according to claim 10 , wherein ions implanted into the first ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F; and ions implanted into the second ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

27 . The micro-LED according to claim 10 , wherein the first ion implantation fence is formed by at least implanting ions into the first type semiconductor layer; and the second ion implantation fence is formed by at least implanting ions into the second type semiconductor layer.

28 . The micro-LED according to claim 10 , wherein a width of the first ion implantation fence is not greater than 50% of a diameter of the first mesa structure; and a width of the second ion implantation fence is not greater than 50% of a diameter of the second mesa structure.

29 . The micro-LED according to claim 28 , wherein the width of the first ion implantation fence is not greater than 200 nm, the diameter of the first mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 100 nm; and

the width of the second ion implantation fence is not greater than 200 nm, the diameter of the second mesa structure is not greater than 2500 nm, and a thickness of the second type semiconductor layer is not greater than 100 nm.

30 . The micro-LED according to claim 9 , wherein a material of the first type semiconductor layer is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN and AlGaN; and a material of the second type semiconductor layer is selected from one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN and AlGaN.

31 . The micro-LED according to claim 1 , further comprising an integrated circuit (IC) backplane under the first type semiconductor layer and a connection structure electrically connecting the IC backplane with the first type semiconductor layer.

32 . The micro-LED according to claim 31 , wherein the connection structure is a connection pillar or a metal bonding layer.

33 . The micro-LED according to claim 31 , further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, an upper surface of the connection structure being connected with the bottom contact and a bottom surface of the connection structure being connected with the IC backplane.

34 . A micro-LED array panel, comprising a plurality of micro-LED according claim 1 .

35 . A micro-LED array panel, comprising,

a first type semiconductor layer formed in the micro-LED array panel;

a first type cap layer formed on the first type semiconductor layer;

a light emitting layer formed on the first type cap layer;

a second type cap layer formed on the light emitting layer; and

a second type semiconductor layer formed on the second type cap layer;

wherein the first type is P type and the second type is N type; and

the first type semiconductor layer comprises multiple mesa structures, multiple trenches and multiple ion implantation fences separated from the mesa structures by the trenches; wherein a top surface of the ion implantation fence is lower than or aligned with a top surface of the first type semiconductor layer; and

the ion implantation fences are formed around the trenches and between adjacent type mesa structures; wherein an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure.

36 . The micro-LED array panel according to claim 35 , wherein the ion implantation fence is formed around the trench, and the trench is formed around the mesa structure.

37 . The micro-LED array panel according to claim 35 , wherein a bottom surface of the ion implantation fence is aligned with or higher than a bottom surface of the first type semiconductor layer.

38 . The micro-LED array panel according to claim 35 , wherein a space between adjacent sidewalls of the mesa structures is not greater than 50% of a diameter of the mesa structure.

39 . The micro-LED array panel according to claim 38 , wherein the space between the adjacent sidewalls of the mesa structures is not greater than 600 nm.

40 . The micro-LED array panel according to claim 35 , wherein the ion implantation fence absorbs lights from the first mesa structure; and the ion implantation fence comprises a light absorption material, wherein the light absorption material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.

41 . The micro-LED array panel according to claim 35 , wherein a thickness of the first type semiconductor layer is greater than a thickness of the second type semiconductor layer.

42 . The micro-LED array panel according to claim 35 , further comprising a bottom isolation layer filled in the trench.

43 . The micro-LED array panel according to claim 42 , wherein a material of the bottom isolation layer is selected from one or more of SiO 2 , SiN x , Al 2 O 3 , AlN, HfO 2 , TiO 2 , or ZrO 2 .

44 . The micro-LED array panel according to claim 35 , wherein ions implanted into the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

45 . The micro-LED array panel according to claim 35 , wherein the ion implantation fence is formed at least by implanting ions into the first type semiconductor layer.

46 . The micro-LED array panel according to claim 35 , wherein a width of the ion implantation fence is not greater than 50% of a diameter of the mesa structure.

47 . The micro-LED array panel according to claim 46 , wherein the width of the ion implantation is not greater than 200 nm, a diameter of the first mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 300 nm.

48 . The micro-LED array panel according to claim 35 , wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

49 . The micro-LED array panel according to claim 35 , further comprising a top contact formed on a top surface of the second type semiconductor layer.

50 . The micro-LED array panel according to claim 35 , further comprising an integrated circuit (IC) backplane formed under the first type semiconductor layer and a connection structure electrically connecting the IC backplane with the first type semiconductor layer.

51 . The micro-LED array panel according to claim 50 , wherein the connection structure is a connection pillar or a metal bonding layer.

52 . The micro-LED array panel according to claim 50 , further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, an upper surface of the connection structure being connected with the bottom contact and a bottom surface of the connection structure being connected with the IC backplane.

53 . The micro-LED array panel according to claim 35 , wherein the trench extends up through a top surface of the first type semiconductor layer to a bottom surface of the first type cap layer.

54 . The micro-LED array panel according to claim 35 , wherein a top surface of the ion implantation fence is lower than or aligned with a top surface of the trench.

55 . The micro-LED array panel according to claim 35 , wherein the trench does not extend up through a top surface of the first type semiconductor layer.

56 . The micro-LED array panel according to claim 55 , wherein the top of the ion implantation fence is higher than or aligned with a top surface of the trench.

57 . The micro-LED array panel according to claim 55 , wherein the top surface of the ion implantation fence is lower than a top surface of the trench.

58 . A method for manufacturing a micro-LED, comprising:

providing an epitaxial structure, wherein the epitaxial structure comprises a first type semiconductor layer, a first type cap layer, a light emitting layer, a second type cap layer, and a second type semiconductor layer sequentially from top to bottom;

patterning the first type semiconductor layer to form a mesa structure, a trench, and a fence;

depositing a bottom contact on the mesa structure; and

performing an ion implantation process into the fence to form an ion implantation fence.

59 . The method according to claim 58 , wherein after patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, the method further comprises:

depositing a bottom isolation layer on the first type semiconductor layer and the bottom contact;

patterning the bottom isolation layer to expose the bottom contact;

depositing metal material on the isolation layer and the bottom contact;

grinding the metal material to a top surface of the bottom isolation layer, to form a connection structure; and

turning the epitaxial structure upside down and bonding the connection structure with an integrated circuit (IC) backplane.

60 . The method according to claim 59 , wherein in depositing metal material on the isolation layer and the bottom contact, a material of the bottom isolation layer is selected from one or more of SiO 2 , SiN x , Al 2 O 3 , AlN, HfO 2 , TiO 2 , or ZrO 2 .

61 . The method according to claim 59 , wherein in providing the epitaxial structure, the epitaxial structure is grown on a substrate.

62 . The method according to claim 61 , wherein turning the epitaxial structure upside down and bonding the connection structure with the IC backplane further comprises:

removing the substrate.

63 . The method according to claim 61 , wherein after turning the epitaxial structure upside down and bonding the connection structure with the IC backplane, the method further comprises:

forming a top contact and a top conductive layer on a top surface of a second type semiconductor layer.

64 . The method according to claim 58 , wherein depositing the bottom contact on the mesa structure further comprises:

forming a protective mask to protect an area where the bottom contact is not deposited;

depositing material of the bottom contact on the protective mask and on the first type semiconductor layer; and

removing the protective mask from the first type semiconductor layer and removing the material on the protective mask, to form the bottom contact on the mesa structure.

65 . The method according to claim 58 , wherein performing an ion implantation process into the fence to form the ion implantation fence further comprises:

forming a protective mask on an area not being ion implanted while leaving the fence exposed;

implanting ions into the fence; and

removing the protective mask.

66 . The method according to claim 65 , wherein in performing the ion implantation process into the fence to form the ion implantation fence, implanting with an energy of 0˜500 Kev.

67 . The method according to claim 65 , wherein in performing the ion implantation process into the fence to form the first ion implantation fence, implanting a dose of 1E10˜9E17.

68 . The method according to claim 65 , wherein in performing the ion implantation process into the fence to form an ion implantation fence, implanting ions into the ion implantation fence selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

69 . The method according to claim 65 , wherein in performing the ion implantation process into the fence to form the ion implantation fence, a width of the ion implantation fence is not greater than 50% of a diameter of the mesa structure.

70 . The method according to claim 65 , wherein in performing the ion implantation process into the fence to form the ion implantation fence, a width of the ion implantation fence is not greater than 200 nm, a diameter of the mesa structure is not greater than 2500 nm, and a thickness of the first type semiconductor layer is not greater than 300 nm.

71 . The method according to claim 58 , wherein in patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, a width of the trench is not greater than 50% of a diameter of the mesa structure.

72 . The method according to claim 58 , wherein a conductive type of the first type semiconductor layer is P type and a conductive type of the second type semiconductor layer is N type, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

73 . The method according to claim 58 , wherein the ion implantation fence comprises a light absorption material.

74 . The method according to claim 73 , wherein the light absorption material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.