IP Library Granted Patent US 11,977,113
Granted Patent B1
US 11,977,113 · App. 18/165,272 · Granted May 7, 2024

Quantum error-correction in microwave integrated quantum circuits

Inventors: William J. Zeng (Berkeley, CA); Eyob A. Sete (Walnut Creek, CA); Chad Tyler Rigetti (Walnut Creek, CA)
Assignee: Rigetti & Co, LLC
G01R31/2851G06N10/00
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Quick Facts
Patent No.
US 11,977,113
App. No.
18/165,272
Granted
May 7, 2024
Kind
B1
Abstract

In a general aspect, a quantum error-correction technique includes applying a first set of two-qubit gates to qubits in a lattice cell, and applying a second, different set of two-qubit gates to the qubits in the lattice cell. The qubits in the lattice cell include data qubits and ancilla qubits, and the ancilla qubits reside between respective nearest-neighbor pairs of the data qubits. After the first and second sets of two-qubit gates have been applied, measurement outcomes of the ancilla qubits are obtained, and the parity of the measurement outcomes is determined.

Claims (43)

1. A method to perform quantum error-correction in a quantum computing system, the quantum computing system comprising a quantum processor cell and a control system communicably coupled to the quantum processor cell, the quantum processor cell comprises a tunable coupler device coupled between a first qubit device and a second qubit device, the first qubit device defining a data qubit and the second qubit device defining an ancilla qubit, the method comprising:

identifying a two-qubit quantum logic gate to be applied to the data qubit and the ancilla qubit in a quantum error-correction scheme;

generating, by operation of the control system, a control sequence configured to apply the two-qubit quantum logic gate, the control sequence comprising a control signal for the tunable coupler device; and

sending the control sequence to the quantum processor cell to execute the two-qubit quantum logic gate.

2. The method of claim 1 , wherein applying the two-qubit quantum logic gate comprises applying an arbitrary iSWAP exponent gate to the data qubit and the ancilla qubit.

3. The method of claim 1 , wherein applying the two-qubit quantum logic gate comprises applying a controlled-not (CNOT) gate to the data qubit and the ancilla qubit.

4. The method of claim 1 , wherein applying the two-qubit quantum logic gate comprises applying a controlled-z (CZ) gate to the data qubit and the ancilla qubit.

5. The method of claim 1 , wherein the control signal causes a magnetic bias field to be applied to the tunable coupler device to tune a resonance frequency of the tunable coupler device.

6. The method of claim 1 , wherein the tunable coupler device is a fluxonium device.

7. The method of claim 1 , wherein the tunable coupler device comprises:

a superconducting circuit loop; and

bias circuitry that applies a magnetic bias field to the superconducting circuit loop in response to the control signal.

8. The method of claim 1 , wherein applying the two-qubit quantum logic gate comprises applying respective microwave pulses to the first and second qubit devices.

9. The method of claim 1 , comprising obtaining a measurement output of the ancilla qubit.

10. The method of claim 1 , wherein the tunable coupler device is a first tunable coupler device, the first qubit device defines a first data qubit, the quantum processor cell comprises a third qubit device and a second tunable coupler device coupled between the second qubit device and the third qubit device, the third qubit device defines a second data qubit, the two-qubit quantum logic gate is a first two-qubit quantum logic gate, the control sequence is a first control sequence, the control signal is a first control signal, and the method comprises:

identifying a second two-qubit quantum logic gate to be applied to the second data qubit and the ancilla qubit in the quantum error-correction scheme;

generating, by operation of the control system, a second control sequence configured to apply the second two-qubit quantum logic gate, the control sequence comprising a second control signal for the tunable coupler device;

sending the second control sequence to the quantum processor cell to execute the second two-qubit quantum logic gate;

obtaining measurement outcomes of the ancilla qubit; and

determine a parity of the measurement outcomes for the quantum error-correction scheme.

11. A quantum computing system comprising:

a quantum processor cell comprising a tunable coupler device between a first qubit device and a second qubit, the first qubit device defining a data qubit and second qubit device defining an ancilla qubit; and

a control system communicably coupled to the quantum processor cell, the control system configured to perform operations comprising:

identifying a two-qubit quantum logic gate to be applied to the data qubit and the ancilla qubit in a quantum error-correction scheme;

generating a control sequence configured to apply the two-qubit quantum logic gate, the control sequence comprising a control signal for the tunable coupler device; and

sending the control sequence to the quantum processor cell to execute the two-qubit quantum logic gate.

12. The system of claim 11 , wherein the two-qubit quantum logic gate comprises an arbitrary iSWAP exponent gate applied to the data qubit and the ancilla qubit.

13. The system of claim 11 , wherein the two-qubit quantum logic gate comprises a controlled-not (CNOT) gate applied to the data qubit and the ancilla qubit.

14. The system of claim 11 , wherein the two-qubit quantum logic gate comprises a controlled-z (CZ) gate applied to the data qubit and the ancilla qubit.

15. The system of claim 11 , wherein the control signal causes a magnetic bias field to be applied to the tunable coupler device to tune a resonance frequency of the tunable coupler device.

16. The system of claim 11 , wherein the tunable coupler device is a fluxonium device.

17. The system of claim 11 , wherein the tunable coupler device comprises:

a superconducting circuit loop; and

bias circuitry that applies a magnetic bias field to the superconducting circuit loop in response to the control signal.

18. The system of claim 11 , wherein applying the two-qubit quantum logic gate comprises applying respective microwave pulses to the first and second qubit devices.

19. The system of claim 11 , wherein the operations comprise:

obtaining a measurement output of the ancilla qubit.

20. The system of claim 11 , wherein the tunable coupler device is a first tunable coupler device, the first qubit device defines a first data qubit, the quantum processor cell comprises a third qubit device and a second tunable coupler device coupled between the second qubit device and the third qubit device, the third qubit device defines a second data qubit, the two-qubit quantum logic gate is a first two-qubit quantum logic gate, the control sequence is a first control sequence, the control signal is a first control signal, and the operations comprise:

identifying a second two-qubit quantum logic gate to be applied to the second data qubit and the ancilla qubit in the quantum error-correction scheme;

generating, by operation of the control system, a second control sequence configured to apply the second two-qubit quantum logic gate, the control sequence comprising a second control signal for the tunable coupler device;

sending the second control sequence to the quantum processor cell to execute the second two-qubit quantum logic gate;

obtaining measurement outcomes of the ancilla qubit; and

determine a parity of the measurement outcomes for the quantum error-correction scheme.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Dec 12, 2024
From: TRINITY CAPITAL INC.
To: RIGETTI & CO, LLC
Reel/Frame 069603/0771 →
RELEASE OF SECURITY INTEREST Recorded Dec 12, 2024
From: TRINITY CAPITAL INC.
To: RIGETTI & CO, LLC; RIGETTI INTERMEDIATE LLC; RIGETTI COMPUTING, INC.
Reel/Frame 069603/0831 →
AMENDED AND RESTATED INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Jul 8, 2024
From: RIGETTI & CO, LLC; RIGETTI INTERMEDIATE LLC; RIGETTI COMPUTING, INC.
To: TRINITY CAPITAL INC.
Reel/Frame 068146/0416 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2023
From: ZENG, WILLIAM J.; SETE, EYOB A.; RIGETTI, CHAD T.; RIGETTI & CO, INC.
To: RIGETTI & CO, LLC
Reel/Frame 062616/0320 →
Continuity (5)
Continuation 17695980 · Mar 16, 2022
Division 17066187 · Oct 8, 2020
Continuation 16424901 · May 29, 2019
Division 15380822 · Dec 15, 2016
Provisional Application 62277256 · Jan 11, 2016