Apparatus and method for synchronous rectifier control delay

1. A circuit for use in an LLC converter with an LLC primary side and an LLC secondary side, the circuit comprising:

a first primary side switch;

a first secondary side switch assembly;

a controller configured to:

measure, on the LLC secondary side, a first voltage comprising an output voltage of the LLC converter;

determine, based on the first voltage, a synchronous rectifier delay due to the first voltage;

adjust the synchronous rectifier delay by a delay margin based on a slew rate of an output current on the LLC secondary side above a current threshold;

apply a first gate voltage to the first primary side switch to transition the first primary side switch from an off state to an on state; and

apply a second gate voltage to the first secondary side switch assembly to transition the first secondary side switch assembly from an off state to an on state;

wherein the application of the first gate voltage and the application of the second gate voltage are separated by the adjusted synchronous rectifier delay.

2. The circuit of claim 1 , wherein the controller, in being configured to determine the synchronous rectifier delay, is configured to apply the first voltage in a linear polynomial equation, the linear polynomial equation based on a linear trend of expected delay values at corresponding first voltage values.

3. The circuit of claim 1 , wherein the controller is further configured to add a default delay to the synchronous rectifier delay prior to applying the second gate voltage.

4. The circuit of claim 1 , wherein the controller is further configured to:

measure, on the LLC primary side, an input voltage;

determine, based on the input voltage, a delay due to the input voltage; and

calculate the synchronous rectifier delay further based on the delay due to the input voltage.

5. The circuit of claim 4 , wherein the controller is further configured to compare the output voltage to a nominal voltage; and

wherein the controller, in being configured to calculate the synchronous rectifier delay, is configured to calculate the synchronous rectifier delay if the output voltage is less than the nominal voltage.

6. The circuit of claim 4 , wherein the controller is further configured to:

set the synchronous rectifier delay to zero if the calculated synchronous rectifier delay is less than zero; and

set the synchronous rectifier delay to a maximum value if the synchronous rectifier delay is above the maximum value.

7. The circuit of claim 1 , wherein the controller is further configured to adjust the synchronous rectifier delay by a frequency output above a frequency threshold.

8. The circuit of claim 1 , wherein the first secondary side switch assembly comprises:

a high side switch coupled to a secondary winding of a transformer; and

a low side switch coupled to the secondary winding of the transformer.

9. The circuit of claim 8 further comprising:

a second primary side switch forming a half bridge configuration with the first primary side switch; and

a second secondary side switch assembly comprising:

a high side switch coupled to the secondary winding; and

a low side switch coupled to the secondary winding.

10. The circuit of claim 9 , wherein the controller is further configured to:

apply a third gate voltage to the first primary side switch to transition the first primary side switch from the on state to the off state;

apply a fourth gate voltage to the first secondary side switch assembly to transition the first secondary side switch assembly from the on state to the off state;

apply a fifth gate voltage to the second primary side switch to transition the second primary side switch from an off state to the on state; and

apply a sixth gate voltage to the second secondary side switch assembly to transition the second secondary side switch assembly from an off state to the on state;

wherein application of the sixth gate voltage occurs after current conduction through the first secondary side switch assembly.

11. A method for adjusting off-to-on time delay between primary and secondary side switches in an LLC converter, the method comprising:

monitoring, on a secondary side of the LLC converter, an output voltage of the LLC converter;

determining, based on the output voltage, a synchronous rectifier delay;

adjusting the synchronous rectifier delay by a delay margin based on a slew rate of an output current on the LLC secondary side above a current threshold;

causing a first primary side switch to transition from an off state to an on state;

delaying a first period of time based on the synchronous rectifier delay; and

causing a first secondary side switch assembly to transition from an off state to an on state after the first period of time.

12. The method of claim 11 , wherein determining comprises applying the output voltage in a polynomial equation based on a trend of expected delay values at corresponding input voltage values.

13. The method of claim 12 , wherein the polynomial equation comprises a monomial equation.

14. The method of claim 11 further comprising:

monitoring a frequency of a compensator output; and

further adjusting the synchronous rectifier delay by the delay margin based on the frequency being above a frequency threshold.

15. The method of claim 14 further comprising:

monitoring, on the LLC primary side, an input voltage; and

adjusting the synchronous rectifier delay based on the input voltage.

16. The method of claim 15 , wherein adjusting comprises:

determining a delay due to the output voltage based on the input voltage;

determining a delay due to the output current based on the output current;

adding the delay due to the input voltage to the synchronous rectifier delay; and

subtracting the delay due to the output current from the synchronous rectifier delay.

17. The method of claim 11 further comprising comparing the output voltage to a nominal voltage.

18. The method of claim 17 further comprising adjusting the synchronous rectifier delay based on a default delay if the output voltage is above the nominal voltage.

19. The method of claim 11 further comprising:

causing the first primary side switch to transition from the on state to the off state;

causing the first secondary side switch assembly to transition from the on state to the off state;

causing a second primary side switch to transition from an off state to an on state prior to cessation of current flow through the first secondary side switch assembly; and

causing a second secondary side switch assembly to transition from an off state to an on state after cessation of current flow through the first secondary side switch assembly.

20. The method of claim 19 further comprising calculating an updated synchronous rectifier delay; and

wherein the transition from the off state to the on state of the second secondary side switch assembly occurs after the updated synchronous rectifier delay.