Granted Patent B2

US 12,635,544 · App. 18/166,192 · Granted May 19, 2026

Inventors: Arun Virupaksha Gowda (Rexford, NY); Ljubisa D. Stevanovic (Clifton Park, NY); Christopher James Kapusta (Delanson, NY); Robert Dwayne Gossman (Clifton Park, NY); Risto Ilkka Sakari Tuominen (Helsinki, FI)

Assignee: General Electric Company

H01L23/49838H01L21/486H01L23/49861

Abstract

Claims (75)

1 . A semiconductor assembly comprising:

a semiconductor device comprising:

an upper surface;

a gate pad disposed on said upper surface; and

at least one source pad disposed on said upper surface; and

a power overlay redistribution layer (POL-RDL) package coupled to said semiconductor device and comprising:

a dielectric layer comprising an upper surface;

at least one source pad disposed on said upper surface of said dielectric layer and electrically coupled to said at least one source pad of said semiconductor device;

at least one contact pad disposed on said upper surface of said dielectric layer; and

at least one trace connection having a resistivity value and electrically coupling said at least one source pad of said POL-RDL package to said at least one contact pad;

wherein said at least one trace connection is made from a first material having a first resistivity value and said at least one contact pad is made from a second material having a second resistivity value, and wherein said first resistivity value is greater than said second resistivity value.

2 . The semiconductor assembly of claim 1 further comprising a gate pad disposed on said upper surface of said dielectric layer and electrically coupled to said gate pad of said semiconductor device.

3 . The semiconductor assembly of claim 1 , wherein said at least one trace connection has a width less than a width of said at least one contact pad, and wherein the width of said trace connection controls the resistivity value of said trace connection.

4 . The semiconductor assembly of claim 1 , wherein said second material is layered over said first material.

5 . The semiconductor assembly of claim 1 further comprising at least one interconnect pad for attaching of electrical leads to said at least one source pad of the POL-RDL package.

6 . The semiconductor assembly of claim 1 , wherein said at least one source pad and said at least one contact pad of said POL-RDL package each comprise attachment pads.

7 . The semiconductor assembly of claim 1 , wherein said POL-RDL package further comprises a gate contact disposed on said dielectric layer; and

an additional trace connection electrically coupling said gate contact to said gate pad of said semiconductor device.

8 . A semiconductor assembly comprising:

a semiconductor device comprising:

an upper surface;

a gate pad disposed on said upper surface; and

at least one source pad disposed on said upper surface; and

a power overlay redistribution layer (POL-RDL) package coupled to said semiconductor device and comprising:

a dielectric layer comprising an upper surface;

at least one source pad disposed on said upper surface of said dielectric layer and electrically coupled to said at least one source pad of said semiconductor device;

at least one contact pad disposed on said upper surface of said dielectric layer; and

at least one trace connection having a resistivity value and electrically coupling said at least one source pad of said POL-RDL package to said at least one contact pad;

wherein said at least one source pad and said at least one contact pad of said POL-RDL package each comprise attachment pads;

wherein said at least one trace connection comprises a resistor mounted to said attachment pads with solder.

9 . A semiconductor assembly comprising:

a semiconductor device comprising:

an upper surface;

a gate pad disposed on said upper surface; and

at least one source pad disposed on said upper surface; and

a power overlay redistribution layer (POL-RDL) package coupled to said semiconductor device and comprising:

a dielectric layer comprising an upper surface;

at least one source pad disposed on said upper surface of said dielectric layer and electrically coupled to said at least one source pad of said semiconductor device;

at least one contact pad disposed on said upper surface of said dielectric layer; and

at least one trace connection having a resistivity value and electrically coupling said at least one source pad of said POL-RDL package to said at least one contact pad;

wherein said semiconductor device comprises a first outer peripheral edge that defines a first surface area, wherein said dielectric layer of said POL-RDL package comprises a second outer peripheral edge that defines a second surface area, wherein the second surface area is greater than the first surface area, and wherein said second outer peripheral edge extends beyond said first outer peripheral edge to define an overhang region.

10 . The semiconductor assembly of claim 9 , wherein said at least one contact pad extends to said first outer peripheral edge.

11 . The semiconductor assembly of claim 9 , wherein said at least one contact pad is at least partially disposed in the overhang region.

12 . The semiconductor assembly of claim 9 , wherein said at least one source pad of said POL-RDL package extends to said first outer peripheral edge.

13 . The semiconductor assembly of claim 9 , wherein said at least one source pad of said POL-RDL package is at least partially disposed in the overhang region.

14 . A method of manufacturing a semiconductor assembly, the method comprising:

coupling a dielectric layer of a power overlay redistribution layer (POL-RDL) package to an upper surface of a semiconductor device, the semiconductor device including at least one source pad and a gate pad disposed on the upper surface;

forming at least one source pad of the POL-RDL package on an upper surface of the dielectric layer;

electrically coupling the at least one source pad of the POL-RDL package to the at least one source pad of the semiconductor device;

forming a gate pad of the POL-RDL package on the upper surface of the dielectric layer;

electrically coupling the gate pad of the POL-RDL package to the gate pad of the semiconductor device;

forming at least one contact pad on the upper surface of the dielectric layer; and

electrically coupling the at least one source pad of the POL-RDL package to the at least one contact pad using at least one trace connection having a resistivity value;

wherein said at least one trace connection is made from a first material having a first resistivity value and said at least one contact pad is made from a second material having a second resistivity value, and wherein said first resistivity value is greater than said second resistivity value.

15 . The method of claim 14 , wherein the at least one trace connection has a width less than a width of the at least one contact pad, and wherein the width of the trace connection controls the resistivity value of the trace connection.

16 . A method of manufacturing a semiconductor assembly, the method comprising:

coupling a dielectric layer of a power overlay redistribution layer (POL-RDL) package to an upper surface of a semiconductor device, the semiconductor device including at least one source pad and a gate pad disposed on the upper surface;

forming at least one source pad of the POL-RDL package on an upper surface of the dielectric layer;

electrically coupling the at least one source pad of the POL-RDL package to the at least one source pad of the semiconductor device;

forming a gate pad of the POL-RDL package on the upper surface of the dielectric layer;

electrically coupling the gate pad of the POL-RDL package to the gate pad of the semiconductor device;

forming at least one contact pad on the upper surface of the dielectric layer; and

electrically coupling the at least one source pad of the POL-RDL package to the at least one contact pad using at least one trace connection having a resistivity value;

wherein the semiconductor device includes a first outer peripheral edge that defines a first surface area, wherein the dielectric layer of the POL-RDL package includes a second outer peripheral edge that defines a second surface area, wherein the second surface area is greater than the first surface area, and wherein the second outer peripheral edge extends beyond the first outer peripheral edge to define an overhang region.

17 . A method of manufacturing a semiconductor assembly, the method comprising:

coupling a dielectric layer of a power overlay redistribution layer (POL-RDL) package to an upper surface of a semiconductor device, the semiconductor device including at least one source pad and a gate pad disposed on the upper surface;

forming at least one source pad of the POL-RDL package on an upper surface of the dielectric layer;

electrically coupling the at least one source pad of the POL-RDL package to the at least one source pad of the semiconductor device;

forming a gate pad of the POL-RDL package on the upper surface of the dielectric layer;

electrically coupling the gate pad of the POL-RDL package to the gate pad of the semiconductor device;

forming at least one contact pad on the upper surface of the dielectric layer; and

electrically coupling the at least one source pad of the POL-RDL package to the at least one contact pad using at least one trace connection having a resistivity value;

further comprising forming attachment pads on the at least one source pad of the POL-RDL package and the at least one contact pad of the dielectric layer.

18 . The method of claim 17 , wherein electrically coupling the at least one source pad of the POL-RDL package to the at least one contact pad using comprises soldering a resistor onto the attachment pads.

19 . The method of claim 18 , wherein the resistor has a resistivity value in the range of 10 mΩ to 100 mΩ.

Assignments (1)

Continuity (1)

References Cited (54)