Systems and methods for efficient and scalable design of battery packs
In one embodiment, a battery monitoring unit for monitoring a battery pack may include a first power MOSFET transistor with at least three pads, and a printed-circuit board with at least three copper layers. The first copper layer may have vias that connect electrical components amounted on the printed-circuit board. The second copper layer may have a first area where copper material is excluded. The first power MOSFET transistor is embedded (1) in the first area of the second copper layer where the copper material is excluded, and (2) between the first copper layer and the third copper layer. The two pads of the power MOSFET may be plated with copper. The first power MOSFET transistor may be connected to the one or more first electrical components through the at least three pads plated with copper.
1 . A battery monitoring unit for monitoring a battery pack, comprising:
a first power MOSFET transistor comprising at least three pads for connecting to one or more first electrical components; and
a printed-circuit board comprising at least a first copper layer, a second copper layer, and a third copper layer, wherein:
the first copper layer comprises a plurality of vias that connect one or more second electrical components that are mounted on a surface of the printed-circuit board;
the second copper layer comprises a first area wherein copper material is excluded for embedding the first power MOSFET transistor, and the first power MOSFET transistor is embedded (1) in the first area of the second copper layer where the copper material is excluded, and (2) between the first copper layer and the third copper layer; and
the at least three pads of the first power MOSFET transistor are plated with copper, and the first power MOSFET transistor is connected to the one or more first electrical components through the at least three pads plated with copper.
2 . The battery monitoring unit of claim 1 , further comprising:
one or more resistors that are embedded in a second area of the second copper layer of the printed-circuit board, wherein the copper material is excluded from the second copper layer of the printed-circuit board.
3 . The battery monitoring unit of claim 1 , wherein the first power MOSFET transistor is connected to the one or more first electrical components through the first copper layer of the printed-circuit board.
4 . The battery monitoring unit of claim 1 , wherein the first power MOSFET transistor is connected to the one or more first electrical components through the first copper layer of the printed-circuit board.
5 . The battery monitoring unit of claim 1 , wherein the first power MOSFET transistor has a thickness dimension that is substantially less than the other two dimensions of the first power MOSFET transistor.
6 . The battery monitoring unit of claim 1 , wherein the first power MOSFET transistor has a first thickness less than a second thickness of the one or more first electrical components.
7 . The battery monitoring unit of claim 1 , further comprising one or more connection pads that are connected to respective connection terminals of a rigid printed-circuit board.
8 . The battery monitoring unit of claim 1 , wherein the battery monitoring unit is implemented as a system-in-package module.
9 . The battery monitoring unit of claim 1 , wherein the battery monitoring unit monitors one or more parameters of one or more battery units in the battery pack.
10 . The battery monitoring unit of claim 1 , wherein the at least three pads that are plated with copper are integrated with respective copper filled laser vias.
11 . The battery monitoring unit of claim 1 , further comprising:
a second power MOSFET transistor having a first thickness, a first width, and a first length; and
a third electrical component other than the first power MOSFET transistor, the third electrical component having a second thickness, a second width, and a second length.
12 . The battery monitoring unit of claim 11 , wherein the second power MOSFET transistor is stacked on the third electrical component.
13 . The battery monitoring unit of claim 12 , wherein the first width of the second power MOSFET transistor is greater than the second width of the third electrical component, and wherein the first length of the second power MOSFET transistor is greater than the second length of the third electrical component.
14 . The battery monitoring unit of claim 13 , wherein the first width of the second power MOSFET transistor is less than the second width of the third electrical component, and wherein the first length of the second power MOSFET transistor is less than the second length of the third electrical component.
15 . The battery monitoring unit of claim 11 , wherein the second power MOSFET transistor is connected to one or more fourth electrical components through wire bounds.
16 . The battery monitoring unit of claim 15 , wherein the wire bounds that connect the second power MOSFET transistor to the one or more fourth electrical components come from one or more wire-bond pads on a top surface of the second power MOSFET transistor.
17 . The battery monitoring unit of claim 11 , wherein the third electrical component is a protection IC.
18 . The battery monitoring unit of claim 11 , wherein the third electrical component is stacked on a top surface of the second power MOSFET transistor.
19 . The battery monitoring unit of claim 18 , wherein the first width of the second power MOSFET transistor is greater than the second width of the third electrical component, wherein the second width of the third electrical component is less than the second length of the second power MOSFET transistor, and wherein the second power MOSFET transistor is connected to one or more fourth electrical components through one or more wire-bond pads on a top surface of the second power MOSFET transistor.
20 . The battery monitoring unit of claim 18 , wherein the second power MOSFET transistor is connected to one or more fourth electrical components through one or more wire-bond pads on a bottom surface of the second power MOSFET transistor.