Memory cell and memory array select transistor
A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.
1. A method of selectively operating a semiconductor device as a memory select transistor with increased on-state drain current, said method comprising:
providing said semiconductor device comprising a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type; a body having said first conductivity type; a source region and a drain region each having said second conductivity type and being separated by said body; and a gate positioned in between said source region and said drain region; wherein said semiconductor device is configured to function as a select transistor for at least one memory element connected to said drain region or said source region, wherein a state of said at least one memory element is determined by a resistivity of said at least one memory element; and
selectively operating said semiconductor device as said semiconductor memory device or said transistor, wherein said selectively operating comprises:
applying a relatively low voltage to said buried layer to operate said semiconductor device as said memory select transistor wherein said memory select transistor operates as an ordinary memory select transistor with a first amount of on-state drain current;
applying a relatively high voltage to said buried layer to operate said semiconductor device as said semiconductor memory device, wherein said semiconductor memory device has at least two stable states; and
applying an intermediate high voltage higher than said relatively low voltage but lower than said relatively high voltage to said buried layer to operate said semiconductor device as said memory select transistor with increased on-state drain current, relative to said first amount of on-state drain current.
2. The method of claim 1 , wherein said relatively high voltage is sufficiently high to turn on a vertical bipolar junction transistor (BJT) formed by said buried layer, said body and one of said source region or said drain region.
3. The method of claim 2 , wherein said turn on of said vertical BJT acts as a base current for a lateral BJT formed by said source region, said body and said drain region, turning on said lateral BJT and resulting in increased on-state drain current.
4. The method of claim 1 , wherein said intermediate high voltage summed with a voltage applied to said gate is sufficiently high to turn on a vertical bipolar junction transistor (BJT) formed by said buried layer, said body and one of said source region or said drain region.
5. The method of claim 4 , wherein said turn on of said vertical BJT acts as a base current for a lateral BJT formed by said source region, said body and said drain region, turning on said lateral BJT and resulting in increased on-state drain current.
6. The method of claim 1 , further comprising governing an amount of on-state drain current enhancement of said semiconductor device functioning as said memory select transistor connected to at least one memory element, by an amount of voltage applied to said buried layer.
7. The method of claim 4 , wherein an off-state current, when said intermediate high voltage is applied, is the same as when zero voltage is applied to said buried layer.
8. The method of claim 1 , comprising applying zero voltage to said gate and applying said intermediate high voltage to said drain region, resulting in turning off a MOS transistor formed by said source region, said gate, said drain region and said body; and turning on a lateral bipolar junction transistor (BJT) formed by said source region, said body and said drain region.
9. The method of claim 8 , comprising switching between on and off of said MOS transistor by controlling an amount of voltage applied to said gate.
10. The method of claim 1 , further comprising providing a charge trap layer containing a substantial number of charge trap centers that may absorb excess majority carrier.
11. The method of claim 1 , further comprising providing a buried layer tap connected to said buried layer.
12. The method of claim 1 , further comprising providing a metal silicide junction located at at least one of: a location between said source region and said body, and a location between said drain region and said body.
13. The method of claim 1 , further comprising providing an energy band offset region located at at least one of: a location between said source region and said body, and a location between said drain region and said body.
14. The method of claim 1 , further comprising providing a recombination center located at at least one of: a location between said source region and said body, and a location between said drain region and said body.
15. The method of claim 1 , wherein said at least one memory element comprises resistive switching memory (RRAM), phase change memory (also known as PCM, PRAM, PCRAM), Chalcogenide memory (CRAM), or magnetoresistive memory (MRAM).
16. The method of claim 1 , wherein at least two of said memory elements are connected to one said memory select transistor for 1T-nM architecture.
17. The method of claim 16 , wherein said at least two memory elements are three-dimensionally stacked.