Paired processing unit architecture for improved microcontroller performance in multi-core processor
An architecture in which the cores of a multicore processor are paired together. An internal memory may be connected to the pair of cores via separate leads. The pair of cores can run at reversed clock phases. A clock generator may be responsible for generating a clock signal that can be provided as input to one core, and a signal inverter may be responsible for inverting the clock signal so as to generate an inverted clock signal that can be provided as input to the other core.
1. A processor comprising:
a plurality of cores that includes at least a first core and a second core;
an internal memory that is connected to the first and second cores via separate leads so as to allow independent access by the first and second cores;
a clock generator that is configured to produce a clock signal that is provided as input to the first core; and
an inverter that is configured to invert the clock signal to generate an inverted clock signal that is provided as input to the second core;
wherein access of the internal memory by the first core is governed by the clock signal while access of the internal memory by the second core is governed by the inverted clock signal.
2. The processor of claim 1 , wherein the first core operates on a rising edge of the clock signal while the second core operates on a rising edge of the inverted clock signal.
3. The processor of claim 1 , wherein the clock signal and the inverted clock signal have complementary phases, thereby ensuring that the internal memory is accessed by either the first core or the second core in each cycle.
4. The processor of claim 1 , wherein the plurality of cores further includes a third core, and wherein the processor further comprises:
a second internal memory that is connected to the second and third cores via separate leads so as to allow independent access by the second and third cores.
5. The processor of claim 4 , wherein the second core is configured to alternately access the internal memory and the second internal memory over successive cycles.
6. The processor of claim 4 , wherein the clock signal is further provided as input to the third core.
7. The processor of claim 6 , wherein access of the second internal memory by the second core is governed by the inverted clock signal while access of the second internal memory by the third core is governed by the clock signal.
8. A method for controlling a multicore processor, the method comprising:
generating a clock signal that is provided to a first core of the multicore processor as input, where the clock signal governs access of an internal memory by the first core;
inverting the clock signal so as to generate an inverted clock signal; and
providing the inverted clock signal to a second core of the multicore processor as input, where the inverted clock signal governs access of the internal memory by the second core.
9. The method of claim 8 , wherein the clock signal and the inverted clock signal have complementary phases, thereby ensuring that the internal memory is accessed by either the first core or the second core in each cycle.
10. The method of claim 8 , wherein the clock signal is produced by a single-phase clock generator that is connected, via separate leads, to (i) the first processing unit and (ii) an inverter that is responsible for inverting the clock signal so as to generate the inverted clock signal.
11. A multicore processor comprising:
an internal memory;
an inverter configured to invert a clock signal that is provided as input so as to generate an inverted clock signal that a reversed phase;
a first core whose access to the internal memory is governed by the clock signal; and
a second core whose access to the internal memory is governed by the inverted clock signal.
12. The multicore processor of claim 11 , further comprising:
a clock generator configured to produce the clock signal.
13. The multicore processor of claim 11 , wherein a falling edge of the clock signal coincides with a rising edge of the inverted clock signal while a rising edge of the clock signal coincides with a falling edge of the inverted clock signal.
14. The multicore processor of claim 11 , wherein the internal memory includes a first bus to which the first core is communicatively connected and a second bus to which the second core is communicatively connected.
15. The multicore processor of claim 11 , wherein the first core is identical to the second core.
16. The multicore processor of claim 11 , wherein the internal memory is one of multiple internal memories included in the multicore processor.
17. The multicore processor of claim 16 , wherein each of the multiple internal memories is shared between a pair of cores.
18. The multicore processor of claim 11 , further comprising:
a second internal memory; and
a third core whose access to the second internal memory is governed by the clock signal.
19. The multicore processor of claim 18 , wherein the second core alternately accesses the internal memory and the second internal memory.
20. The multicore processor of claim 11 , wherein the first and second cores are connected to the internal memory via separate leads.