Photonic integrated circuit system and method of fabrication
A photonic integrated circuit (PIC) system, preferably including a substrate, one or more photonic connections, and a plurality of circuit blocks. The circuit blocks preferably include one or more waveguides that are optically coupled to the photonic connections, such as by transition features. A method of PIC fabrication, preferably including defining a PIC structure and defining circuit blocks. The circuit blocks are preferably defined onto one or more template regions defined by the PIC structure. Photonic connections are preferably defined as part of the PIC structure. Transition features, such as transitions between the photonic connections and the circuit blocks, are preferably defined concurrently with defining the circuit blocks.
1. A method of fabricating a photonic integrated circuit (PIC) system, comprising:
lithographically defining a PIC structure on a substrate using a first lithographic patterning technique, the PIC structure comprising:
a plurality of circuit block regions; and
a set of connecting waveguides, each connecting waveguide of the set of connecting waveguides having a first width, and optically coupling respective circuit block regions of the plurality of circuit block regions; and
lithographically defining a photonic circuit block within each circuit block region using a second lithographic patterning technique, each photonic circuit block comprising:
a respective transition waveguide having a second width, less than the first width, and
optically coupled to a corresponding connecting waveguide;
a respective transition feature extending between the respective transition waveguide and the corresponding connecting waveguide, tapering from the first width to the second width; and
a photonic circuit element optically coupled to the respective transition waveguide;
wherein defining each respective transition feature comprises providing a tapered masked feature over each connecting waveguide configured to define each respective transition feature; and
wherein each tapered masked feature has a maximum width greater than the first width, and extends past the first width in both directions.
2. The method according to claim 1 , wherein each tapered masked features extends past the first width in each direction by an amount greater than 10 nm.
3. The method according to claim 1 , wherein each tapered masked features extends past the first width in each direction by an amount greater than 30 nm.
4. The method according to claim 1 , wherein each respective transition feature has a linear profile.
5. The method according to claim 1 , wherein each respective transition feature has a curved profile.
6. The method according to claim 1 , wherein each respective transition feature has a quadratic profile.
7. The method according to claim 1 , wherein each respective transition feature defines an adiabatic taper.
8. The method according to claim 1 , wherein each respective transition waveguide is not substantially collinear with the corresponding connecting waveguide.
9. The method of claim 1 , wherein: each connecting waveguide a multi-mode waveguide; and each transition waveguide is a single-mode waveguide.
10. The method of claim 1 , wherein, for each of the plurality of circuit block regions is substantially uniform, before lithographically defining each photonic circuit block.
11. The method of claim 1 , wherein each photonic circuit block is substantially identical.
12. The method of claim 1 , wherein the first lithographic patterning technique is different than the second lithographic patterning technique.
13. The method of claim 12 , wherein the second lithographic patterning technique is selected from a group comprising: stepper photolithography, electron beam lithography, and holographic lithography.
14. The method of claim 13 , wherein the first lithographic patterning technique comprises a contact lithography technique, a nanoimprint lithography technique or a direct write lithography technique.
15. The method of claim 1 , wherein: the PIC structure is defined within a layer on the substrate; and for each circuit block region of the plurality, the photonic circuit block is defined within the layer.
16. The method of claim 15 , wherein the substrate is a silicon-on-insulator substrate, and wherein the layer is a silicon layer.