RF frequency multiplier without balun
Radio frequency (RF) mixer circuits having a complementary frequency multiplier module that requires no balun to multiply a lower frequency base oscillator signal to a higher frequency local oscillator (LO) signal, and which has a significantly reduced IC area compared to balun-based frequency multipliers. In one embodiment, the complementary frequency multiplier module includes a complementary pair of FETs controlled by an applied base oscillator signal. The complementary FETs are coupled to a common-gate FET amplifier and alternate becoming conductive in response to the base oscillator signal. The alternating switching of the complementary FETs in response to the opposing phases of the base oscillator signal cause the common-gate FET amplifier to output a higher frequency local oscillator (LO) signal. The LO signal is coupled to the LO input of a mixer or mixer core of a type suitable for use in conjunction with a frequency multiplier.
1. A radio frequency mixer driver circuit, including:
(a) an input configured to receive an unbalanced applied lower frequency base oscillator signal;
(b) a first complementary frequency multiplier module coupled to the input and configured to generate a first output signal at a higher frequency than the applied lower frequency base oscillator signal, the first complementary frequency multiplier module including:
(1) an N-type transistor including a gate controlled by the applied lower frequency base oscillator signal, a drain configured to be coupled to a first voltage potential, and a source;
(2) a P-type transistor including a gate controlled by the applied lower frequency base oscillator signal, a source configured to be coupled to the first voltage potential, and a drain; and
(3) a first amplifier including a source coupled to the source of the N-type transistor and to the drain of the P-type transistor, and including a drain;
(c) a second complementary frequency multiplier module coupled to the input and configured to generate a second output signal at a higher frequency than the applied lower frequency base oscillator signal, the second complementary frequency multiplier module including:
(1) an N-type transistor including a gate controlled by the applied lower frequency base oscillator signal, a source configured to be coupled to a second voltage potential, and a drain;
(2) a P-type transistor including a gate controlled by the applied lower frequency base oscillator signal, a drain configured to be coupled to the second voltage potential, and a source; and
(3) a second amplifier including a source coupled to the drain of the N-type transistor and to the source of the P-type transistor, and including a drain; and
(d) a parallel resonant filter/coupling circuit including a first input coupled to the drain of the first amplifier to receive the first output signal and a second input coupled to the drain of the second amplifier to receive the second output signal, the parallel resonant filter/coupling circuit being configured to provide a high impedance to the frequency of the first and second output signals and a low impedance at other frequencies, to provide a DC short between the first and second complementary frequency multiplier modules, to output the first and second output signals as balanced first and second output signals having opposite phasing, and to provide a ground return path to circuit ground for current from intermediate frequencies applied to the first and second inputs of the parallel resonant filter/coupling circuit.
2. The radio frequency mixer driver circuit of claim 1 , wherein the parallel resonant filter/coupling circuit includes:
(a) a first inductor and a second inductor series coupled between the first input and the second input of the parallel resonant filter/coupling circuit;
(b) a capacitor coupled between the first input and the second input of the parallel resonant filter/coupling circuit and in parallel with the first and a second inductors; and
(c) a shunt capacitor coupled between circuit ground and a node between the first and a second inductors.
3. The radio frequency mixer driver circuit of claim 1 , wherein the DC short provides a common bias current for the N-type and P-type transistors in the first and second complementary frequency multiplier modules.
4. The radio frequency mixer driver circuit of claim 1 , wherein the first output signal and the second output signal are at twice the frequency of the applied lower frequency base oscillator signal.
5. The radio frequency mixer driver circuit of claim 1 , wherein the N-type transistor and P-type transistor each comprise one or more series-coupled FET devices.
6. The radio frequency mixer driver circuit of claim 1 , wherein the first and second amplifiers are common-gate FET amplifiers.
7. An integrated circuit transmitter and/or receiver including a signal path including at least one of a receiver path Rx or a transmitter path Tx, the signal path including at least one frequency mixer circuit configured to shift signals from a first frequency range to a second frequency range, wherein at least one frequency mixer circuit includes:
(a) an input configured to receive an applied lower frequency base oscillator signal having a first phase;
(b) a first complementary frequency multiplier module coupled to the input and configured to generate a first output signal at a higher frequency than the applied lower frequency base oscillator signal, the first complementary frequency multiplier module including:
(1) an N-type transistor including a gate controlled by the applied lower frequency base oscillator signal, a drain configured to be coupled to a first voltage potential, and a source;
(2) a P-type transistor including a gate controlled by the applied lower frequency base oscillator signal, a source configured to be coupled to the first voltage potential, and a drain; and
(3) a first amplifier including a source coupled to the source of the N-type transistor and to the drain of the P-type transistor, and including a drain; and
(c) a second complementary frequency multiplier module coupled to the input and configured to generate a second output signal at a higher frequency than the applied lower frequency base oscillator signal, the second complementary frequency multiplier module including:
(1) an N-type transistor including a gate controlled by the applied lower frequency base oscillator signal, a source configured to be coupled to a second voltage potential, and a drain;
(2) a P-type transistor including a gate controlled by the applied lower frequency base oscillator signal, a drain configured to be coupled to the second voltage potential, and a source; and
(3) a second amplifier including a source coupled to the drain of the N-type transistor and to the source of the P-type transistor, and including a drain;
(d) a parallel resonant filter/coupling circuit including a first input coupled to the drain of the first amplifier to receive the first output signal and a second input coupled to the drain of the second amplifier to receive the second output signal, the parallel resonant filter/coupling circuit being configured to provide a high impedance to the frequency of the first and second output signals and a low impedance at other frequencies, to provide a DC short between the first and second complementary frequency multiplier modules, to output the first and second output signals as balanced first and second output signals having opposite phasing, and to provide a ground return path to circuit ground for current from intermediate frequencies applied to the first and second inputs of the parallel resonant filter/coupling circuit; and
(e) a mixer core having a first input node coupled without a balun to the first output and the parallel resonant filter/coupling circuit, and a second input node coupled without a balun to the second output and the parallel resonant filter/coupling circuit.
8. The integrated circuit transmitter and/or receiver of claim 7 , wherein the parallel resonant filter/coupling circuit includes:
(a) a first inductor and a second inductor series coupled between the first input and the second input of the parallel resonant filter/coupling circuit;
(b) a capacitor coupled between the first input and the second input of the parallel resonant filter/coupling circuit and in parallel with the first and a second inductors; and
(c) a shunt capacitor coupled between circuit ground and a node between the first and a second inductors.
9. The integrated circuit transmitter and/or receiver of claim 8 , wherein the parallel resonant filter/coupling circuit provides a ground return for an intermediate frequency signal from the mixer core.
10. The integrated circuit transmitter and/or receiver of claim 8 , wherein the DC short provides a common bias current for the N-type and P-type transistors in the first and second complementary frequency multiplier modules.
11. The integrated circuit transmitter and/or receiver of claim 7 , wherein the higher frequency is twice the frequency of the applied lower frequency base oscillator signal.
12. The integrated circuit transmitter and/or receiver of claim 7 , wherein the mixer core includes:
(a) a balun having a first port and a second port on a balanced side, and a third port and a fourth port on an unbalanced side; and
(b) a mixer ring having a first node coupled to the first output signal and the parallel resonant filter/coupling circuit, a second node coupled to the second output signal and the parallel resonant filter/coupling circuit, a third node coupled to the first port of the balun, and a fourth node coupled to the second port of the balun.
13. The integrated circuit transmitter and/or receiver of claim 12 , wherein the mixer ring is a diode-ring.
14. The integrated circuit transmitter and/or receiver of claim 12 , wherein the mixer ring is a quad-FET ring.
15. The integrated circuit transmitter and/or receiver of claim 12 , further including a first filter between the third node of the mixer ring and the first port of the balun, and a second filter between the fourth node of the mixer ring and the second port of the balun.
16. The integrated circuit transmitter and/or receiver of claim 7 , wherein the integrated circuit transmitter and/or receiver is part of a radio frequency wireless device.
17. The integrated circuit transmitter and/or receiver of claim 7 , wherein the N-type transistor and P-type transistor each comprise one or more series-coupled FET devices.
18. The integrated circuit transmitter and/or receiver of claim 7 , wherein the first and second amplifiers are each common-gate FET amplifiers.
19. The integrated circuit transmitter and/or receiver of claim 18 , wherein the common-gate FET amplifiers include a stack of series-coupled FET devices.
20. A radio frequency mixer driver circuit, including:
(a) an input configured to receive an unbalanced applied lower frequency base oscillator signal;
(b) a first complementary frequency multiplier module coupled to the input and configured to generate a first output signal at a higher frequency than the applied lower frequency base oscillator signal, the first complementary frequency multiplier module including:
(1) an N-type transistor including a gate controlled by the applied lower frequency base oscillator signal, a drain configured to be coupled to a first voltage potential, and a source;
(2) a P-type transistor including a gate controlled by the applied lower frequency base oscillator signal, a source configured to be coupled to the first voltage potential, and a drain; and
(3) a first amplifier including a source coupled to the source of the N-type transistor and to the drain of the P-type transistor, and including a drain;
(c) a second complementary frequency multiplier module coupled to the input and configured to generate a second output signal at a higher frequency than the applied lower frequency base oscillator signal, the second complementary frequency multiplier module including:
(1) an N-type transistor including a gate controlled by the applied lower frequency base oscillator signal, a source configured to be coupled to a second voltage potential, and a drain;
(2) a P-type transistor including a gate controlled by the applied lower frequency base oscillator signal, a drain configured to be coupled to the second voltage potential, and a source; and
(3) a second amplifier including a source coupled to the drain of the N-type transistor and to the source of the P-type transistor, and including a drain; and
(d) a parallel resonant filter/coupling circuit including:
(1) a first input coupled to the drain of the first amplifier to receive the first output signal;
(2) a second input coupled to the drain of the second amplifier to receive the second output signal;
(3) a first inductor and a second inductor series coupled between the first input and the second input of the parallel resonant filter/coupling circuit;
(4) a capacitor coupled between the first input and the second input of the parallel resonant filter/coupling circuit and in parallel with the first and a second inductors; and
(5) a shunt capacitor coupled between circuit ground and a node between the first and a second inductors;
wherein the parallel resonant filter/coupling circuit is configured to filter out harmonic frequencies from the first and second output signals, to provide a DC short between the first and second complementary frequency multiplier modules, to output the first and second output signals as balanced first and second output signals having opposite phasing, and to provide a ground return path to circuit ground for current from intermediate frequencies applied to the first and second inputs of the parallel resonant filter/coupling circuit.