IP Library Granted Patent US 11,960,743
Granted Patent B2
US 11,960,743 · App. 18/178,629 · Granted Apr 16, 2024

Memory system with multiple striping of RAID groups and method for performing the same

Inventor: Jon C. R. Bennett (Sudbury, MA)
Assignee: INNOVATIONS IN MEMORY LLC
G06F3/064G06F3/0619G06F3/0689G06F11/1068G06F11/108G11B20/1833G11C29/52G06F3/0611G06F3/0659G06F12/0246G11B2220/60G11C7/1072
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Quick Facts
Patent No.
US 11,960,743
App. No.
18/178,629
Granted
Apr 16, 2024
Kind
B2
Abstract

A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.

Claims (32)

1. A memory system, comprising:

a processor in communication with a plurality of memory modules; and

a group of memory modules of the plurality of memory modules;

the processor is configured to receive data;

the processor is configured to determine redundancy data for the received data;

the processor is configured to store the received data and the redundancy data in one or more memory modules of the group of memory modules;

the processor is configured to receive a read data request; and

on a condition that a write data operation or an erase data operation prevents a read data operation on the one or more memory modules where the requested data is stored, the processor is configured to read sufficient stored data and redundancy data from other memory modules of the group of memory modules to reconstruct the requested data, without waiting for a completion of the write data operation or the erase data operation.

2. The memory system of claim 1 , wherein the processor is configured to perform the write data operation or the erase data operation such that, responsive to the received read data request, data in response to the read data request is provided without a time delay due to the write data operation or the erase data operation.

3. The memory system of claim 1 , wherein the processor is configured to reconstruct the data of a first memory module of the group of memory modules that is a failed memory module.

4. The memory system of claim 3 , wherein the reconstruction of the data of the failed memory module is performed by storing the reconstructed data to another memory module that is not part of the group of memory modules comprising the failed memory module.

5. The memory system of claim 4 , wherein when a further memory module of the plurality of memory modules fails, a policy governs which of the groups of memory modules is reconstructed first.

6. The memory system of claim 5 , wherein the policy is to minimize a probability that data is lost by a subsequent memory module failure.

7. The memory system of claim 5 , wherein the policy is that the reconstruction is performed so that a duration of a degradation of read latency time is minimized.

8. The memory system of claim 1 , wherein when a number of write data operations or erase data operations to the group of memory modules exceeds a time available to perform the operations in a substantially non-overlapping manner on the group of memory modules, write data operations or erase data operations are performed to all of the memory modules of the group of memory modules in a substantially overlapping manner.

9. The memory system of claim 1 , wherein the redundancy data is single parity data or dual parity data.

10. The memory system of claim 1 , wherein the group of memory modules is configured as a RAID (Redundant Array of Independent Disks) group.

11. A method of storing and reading data in a memory system, the method comprising:

receiving, by a processor of the memory system, data;

determining, by the processor, redundancy data for the received data;

storing, by the processor, the received data and the redundancy data in one or more memory modules of a group of memory modules;

receiving, by the processor, a read data request; and

on a condition that a write data operation or an erase data operation prevents a read data operation on the one or more memory modules where the requested data is stored, reading, by the processor, sufficient stored data and redundancy data from other memory modules of the group of memory modules to reconstruct the requested data, without waiting for a completion of the write data operation or the erase data operation.

12. The method of claim 11 , further comprising performing the write data operation or the erase data operation such that, responsive to the received read data request, data in response to the read data request is provided without a time delay due to the write data operation or the erase data operation.

13. The method of claim 11 , further comprising reconstructing the data of a first memory module of the group of memory modules that is a failed memory module.

14. The method of claim 13 , wherein the reconstruction of the data of the failed memory module is performed by storing the reconstructed data to another memory module that is not part of the group of memory modules comprising the failed memory module.

15. The method of claim 14 , wherein when a further memory module of the plurality of memory modules fails, a policy governs which of the groups of memory modules is reconstructed first.

16. The method of claim 15 , wherein the policy is to minimize a probability that data is lost by a subsequent memory module failure.

17. The method of claim 15 , wherein the policy is that the reconstruction is performed so that a duration of a degradation of read latency time is minimized.

18. The method of claim 11 , wherein when a number of write data operations or erase data operations to the group of memory modules exceeds a time available to perform the operations in a substantially non-overlapping manner on the group of memory modules, performing write data operations or erase data operations to all of the memory modules of the group of memory modules in a substantially overlapping manner.

19. The method of claim 11 , wherein the redundancy data is single parity data or dual parity data.

20. The method of claim 11 , wherein the group of memory modules is configured as a RAID (Redundant Array of Independent Disks) group.

Assignments (2)
CORRECTIVE ASSIGNMENT TO REMOVE US PATENT NO. 9013874 PREVIOUSLY RECORDED UNDER REEL AND FRAME 064272/0249. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 17, 2024
From: VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC)
To: INNOVATIONS IN MEMORY LLC
Reel/Frame 068998/0780 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2023
From: VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC)
To: INNOVATIONS IN MEMORY LLC
Reel/Frame 064272/0249 →