Δ-Σ AD converter and sensor device
The present invention provides a ΔΣ AD converter and a sensor device having a small circuit scale and high conversion accuracy. A ΔΣ AD converter includes a ΔΣ AD modulator, an accumulator, a counter, an adjustment value storage part, a first adder, a cumulative value latch part, and a control circuit. The control circuit outputs to the adjustment value storage part a signal designating a temperature range according to the adjustment cumulative value received from the first adder in a case where the count value received from the counter reaches a predetermined value. The adjustment value storage part outputs the adjustment value of the offset value and the adjustment value of the count value according to the signal to the first adder and the counter. The control circuit outputs the latch signal to the cumulative value latch part in response to completion of counting by the counter.
1. A ΔΣ AD converter which converts an input analog signal into a digital signal, the ΔΣ AD converter comprising:
a ΔΣ AD modulator which receives the analog signal and outputs a modulated signal;
an accumulator which accumulates the modulated signal and outputs a cumulative value;
a counter which counts a set count value;
an adjustment value storage part which stores an adjustment value of the count value and an adjustment value of an offset value;
a first adder which outputs an adjustment cumulative value obtained by adding the cumulative value and the adjustment value of the offset value;
a cumulative value latch part which receives the adjustment cumulative value; and
a control circuit which receives the adjustment cumulative value, the count value from the counter, and a threshold value of the adjustment cumulative value for determining a temperature range from the adjustment value storage part, and outputs a control signal to the counter and a latch signal to the cumulative value latch part,
wherein the control circuit determines the temperature range according to the adjustment cumulative value received from the first adder in a case where the count value received from the counter reaches a predetermined value, and outputs a signal designating the temperature range to the adjustment value storage part,
the adjustment value storage part outputs the adjustment value of the offset value and the adjustment value of the count value according to the designated temperature range to the first adder and the counter, and
the control circuit outputs the latch signal to the cumulative value latch part in response to completion of counting by the counter.
2. The ΔΣ AD converter according to claim 1 , wherein the adjustment value of the count value of the adjustment value storage part is an adjustment count value including the predetermined value.
3. The ΔΣ AD converter according to claim 2 , further comprising:
a count value storage part which stores an initial value of the count value to be set in the counter; and
a multiplexer which selects the adjustment count value and the initial value of the count value and outputs them to the counter,
wherein the control circuit outputs a control signal for selecting the adjustment count value and the initial value of the count value to the multiplexer, and outputs a control signal for loading the count value output by the multiplexer or counting the set count value to the counter.
4. The ΔΣ AD converter according to claim 3 , further comprising:
an offset value storage part which stores an initial value of the offset value; and
a third adder which outputs an adjustment offset value obtained by adding the adjustment value of the offset value and the initial value of the offset value,
wherein the first adder outputs the adjustment cumulative value obtained by adding the cumulative value and the adjustment offset value.
5. The ΔΣ AD converter according to claim 2 , further comprising:
an offset value storage part which stores an initial value of the offset value; and
a third adder which outputs an adjustment offset value obtained by adding the adjustment value of the offset value and the initial value of the offset value,
wherein the first adder outputs the adjustment cumulative value obtained by adding the cumulative value and the adjustment offset value.
6. The ΔΣ AD converter according to claim 1 , further comprising:
a second adder which outputs an adjustment count value obtained by adding the count value of the counter and the adjustment value of the count value to the counter.
7. The ΔΣ AD converter according to claim 6 , further comprising:
a count value storage part which stores an initial value of the count value to be set in the counter; and
a multiplexer which selects the adjustment count value and the initial value of the count value and outputs them to the counter,
wherein the control circuit outputs a control signal for selecting the adjustment count value and the initial value of the count value to the multiplexer, and outputs a control signal for loading the count value output by the multiplexer or counting the set count value to the counter.
8. The ΔΣ AD converter according to claim 7 , further comprising:
an offset value storage part which stores an initial value of the offset value; and
a third adder which outputs an adjustment offset value obtained by adding the adjustment value of the offset value and the initial value of the offset value,
wherein the first adder outputs the adjustment cumulative value obtained by adding the cumulative value and the adjustment offset value.
9. The ΔΣ AD converter according to claim 6 , further comprising:
an offset value storage part which stores an initial value of the offset value; and
a third adder which outputs an adjustment offset value obtained by adding the adjustment value of the offset value and the initial value of the offset value,
wherein the first adder outputs the adjustment cumulative value obtained by adding the cumulative value and the adjustment offset value.
10. The ΔΣ AD converter according to claim 1 , further comprising:
an offset value storage part which stores an initial value of the offset value; and
a third adder which outputs an adjustment offset value obtained by adding the adjustment value of the offset value and the initial value of the offset value,
wherein the first adder outputs the adjustment cumulative value obtained by adding the cumulative value and the adjustment offset value.
11. A sensor device comprising:
a sensor element which outputs an analog signal corresponding to measured physical information; and
the ΔΣ AD converter according to claim 1 which receives the analog signal.
12. The sensor device according to claim 11 , wherein the adjustment value of the count value of the adjustment value storage part is an adjustment count value including the predetermined value.
13. The sensor device according to claim 11 , wherein the ΔΣ AD converter further comprises a second adder which outputs an adjustment count value obtained by adding the count value of the counter and the adjustment value of the count value to the counter.