Semiconductor device and method of manufacturing the same

1. A semiconductor device, comprising:

a semiconductor substrate, comprising a first device region and a second device region;

a first semiconductor stack, disposed on the semiconductor substrate over the first device region, wherein the first semiconductor stack has first channels;

a second semiconductor stack, disposed on the semiconductor substrate over the second device region, wherein the second semiconductor stack has second channels, and a total number of the first channels is greater than a total number of the second channels, wherein the second semiconductor stack further comprises a dummy channel disposed on a topmost second channel included in the second semiconductor stack, and the dummy channel is substantially aligned with a topmost first channel included in the first semiconductor stack along a direction perpendicular to the stacking direction of the first semiconductor stack and the semiconductor substrate;

a first gate structure, enclosing the first semiconductor stack; and

a second gate structure, enclosing the second semiconductor stack.

2. The semiconductor device of claim 1 , wherein along a stacking direction of the first semiconductor stack and the semiconductor substrate, a bottommost first channel included in the first semiconductor stack is substantially aligned with a bottommost second channel included in the second semiconductor stack.

3. The semiconductor device of claim 1 , further comprising:

first source and drain regions, disposed at opposite sides of the first gate structure and connected to the first channels of the first semiconductor stack; and

second source and drain regions, disposed at opposite sides of the second gate structure and connected to the second channels of the second semiconductor stack,

wherein the first source and drain regions are in contact with the semiconductor substrate, the second source and drain regions are in contact with the semiconductor substrate, and a full height of the first source and drain regions is greater than a full height of the second source and drain regions.

4. The semiconductor device of claim 3 , further comprising:

a first dielectric layer, disposed between the first source and drain regions and the semiconductor substrate; and

a second dielectric layer, disposed between the second source and drain regions and the semiconductor substrate.

5. The semiconductor device of claim 3 ,

wherein first top surfaces of the first source and drain regions are leveled with a surface of a topmost first channel of the first channels, first bottom surfaces of the first source and drain regions are in contact with a surface of the semiconductor substrate, and the first top surfaces of the first source and drain region are opposite to the first bottom surfaces of the first source and drain regions in a stacking direction of the first source and drain regions and the semiconductor substrate, and

wherein second bottom surfaces of the second source and drain regions are in contact with a surface of the semiconductor substrate, and the second top surfaces of the second source and drain region are opposite to the second bottom surfaces of the second source and drain regions in a stacking direction of the second source and drain regions and the semiconductor substrate.

6. The semiconductor device of claim 1 , wherein the first semiconductor stack includes at least one more channel than the second semiconductor stack.

7. The semiconductor device of claim 1 , wherein a vertical thickness of each peripheral region of the first channels is greater than a vertical thickness of each central region of the first channels, respectively.

8. The semiconductor device of claim 1 , wherein a vertical thickness of each peripheral region of the second channels is greater than a vertical thickness of each central region of the second channels, respectively.

9. The semiconductor device of claim 1 , further comprising:

first inner spacers, each pair of the first inner spacers being disposed between two any adjacent first channels of the first channels and at two opposite sidewalls of a respective portion of the first gate structure, wherein a vertical size of each pair of the first inner spacers is less than a vertical size of the respective portion of the first gate structure; and

second inner spacers, each pair of the second inner spacers being disposed between two any adjacent second channels of the second channels and at two opposite sidewalls of a respective portion of the second gate structure, wherein a vertical size of each pair of the second inner spacers is less than a vertical size of the respective portion of the second gate structure.

10. A semiconductor device, comprising:

a semiconductor substrate;

a first transistor, disposed over the semiconductor substrate, comprising:

a first pair of source and drain regions;

first semiconductor channels, vertically stacked over each other and extending from the source region of the first pair to the drain region of the first pair, wherein topmost surfaces of the first source and drain regions are substantially coplanar to a topmost surface of a topmost layer of the first channels, and bottommost surfaces of the first source and drain regions are in contact with the semiconductor substrate; and

a first gate structure, stacked on and extending in between the first semiconductor channels; and

a second transistor, disposed over the semiconductor substrate, comprising:

a second pair of source and drain regions;

second semiconductor channels, vertically stacked over each other and extending from the source region of the second pair to the drain region of the second pair, wherein topmost surfaces of the second source and drain regions are substantially coplanar to a topmost surface of a topmost layer of the second channels, and bottommost surfaces of the second source and drain regions are in contact with the semiconductor substrate; and

a second gate structure, stacked on and extending in between the second semiconductor channels,

wherein a total number of the first semiconductor channels is greater than a total number of the second semiconductor channels.

11. The semiconductor device of claim 10 , wherein the second transistor further comprises:

a dummy semiconductor channel, stacked over the second semiconductor channels; and

gate spacers, laterally contacting the second gate structure and the dummy semiconductor channel.

12. The semiconductor device of claim 10 , wherein a bottom surface of a topmost channel of the first semiconductor channels is at a level height over the semiconductor substrate higher than a level height of a top surface of a topmost channel of the second semiconductor channels,

wherein the bottom surface is the surface of the topmost channel closest to the semiconductor substrate and the top surface is the surface of the topmost channel farthest away from the semiconductor substrate.

13. The semiconductor device of claim 10 ,

wherein a vertical thickness of each peripheral region of the first semiconductor channels is greater than a vertical thickness of each central region of the first semiconductor channels, respectively, and

wherein a vertical thickness of each peripheral region of the second semiconductor channels is greater than a vertical thickness of each central region of the second semiconductor channels, respectively.

14. The semiconductor device of claim 10 ,

wherein the first transistor further comprises:

first inner spacers, each pair of the first inner spacers being disposed between two any adjacent first channels of the first channels and at two opposite sidewalls of a respective portion of the first gate structure, wherein a vertical size of each pair of the first inner spacers is less than a vertical size of the respective portion of the first gate structure, and

wherein the second transistor further comprises:

second inner spacers, each pair of the second inner spacers being disposed between two any adjacent second channels of the second channels and at two opposite sidewalls of a respective portion of the second gate structure, wherein a vertical size of each pair of the second inner spacers is less than a vertical size of the respective portion of the second gate structure.

15. A semiconductor device, comprising:

a semiconductor substrate, comprising a first device region and a second device region;

a first semiconductor stack, disposed on the semiconductor substrate over the first device region, wherein the first semiconductor stack has first channels;

a second semiconductor stack, disposed on the semiconductor substrate over the second device region, wherein the second semiconductor stack has second channels, and a total number of the first channels is greater than a total number of the second channels;

a first gate structure, enclosing the first semiconductor stack;

a second gate structure, enclosing the second semiconductor stack;

first source and drain regions, disposed at opposite sides of the first gate structure and connected to the first channels of the first semiconductor stack, wherein sidewalls of the first channels are substantially aligned to each other in a stacking direction of the first channels, topmost surfaces of the first source and drain regions are substantially coplanar to a topmost surface of a topmost layer of the first channels, and bottommost surfaces of the first source and drain regions are in contact with the semiconductor substrate, wherein the topmost layer of the first channels is away from the semiconductor substrate; and

second source and drain regions, disposed at opposite sides of the second gate structure and connected to the second channels of the second semiconductor stack, wherein sidewalls of the second channels are substantially aligned to each other in a stacking direction of the second channels, topmost surfaces of the second source and drain regions are substantially coplanar to a topmost surface of a topmost layer of the second channels, and bottommost surfaces of the second source and drain regions are in contact with the semiconductor substrate, wherein the topmost layer of the second channels is away from the semiconductor substrate.

16. The semiconductor device of claim 15 , wherein the second transistor further comprises:

a dummy semiconductor channel, stacked over the second semiconductor channels, wherein the dummy semiconductor channel is free from the second source and drain regions; and

gate spacers, laterally contacting the second gate structure and the dummy semiconductor channel.

17. The semiconductor device of claim 16 , wherein a portion of the second gate structure interposed between the dummy semiconductor channel and the topmost layer of the second channels is free from the second source and drain regions.

18. The semiconductor device of claim 15 ,

wherein a vertical thickness of each peripheral region of the first semiconductor channels is greater than a vertical thickness of each central region of the first semiconductor channels, respectively, and

wherein a vertical thickness of each peripheral region of the second semiconductor channels is greater than a vertical thickness of each central region of the second semiconductor channels, respectively.

19. The semiconductor device of claim 15 ,

wherein the first transistor further comprises:

first inner spacers, each pair of the first inner spacers being disposed between two any adjacent first channels of the first channels and at two opposite sidewalls of a respective portion of the first gate structure, wherein a vertical size of each pair of the first inner spacers is less than a vertical size of the respective portion of the first gate structure, and

wherein the second transistor further comprises:

second inner spacers, each pair of the second inner spacers being disposed between two any adjacent second channels of the second channels and at two opposite sidewalls of a respective portion of the second gate structure, wherein a vertical size of each pair of the second inner spacers is less than a vertical size of the respective portion of the second gate structure.

20. The semiconductor device of claim 1 ,

wherein a portion of the first gate structure laterally covered by the first source and drain regions has a lateral size less than a lateral size of an underlying first channel included in the first semiconductor stack and a lateral size of an overlying first channel included in the first semiconductor stack,

wherein a portion of the second gate structure laterally covered by the second source and drain regions has a lateral size less than a lateral size of an underlying second channel included in the second semiconductor stack and a lateral size of an overlying second channel included in the second semiconductor stack.