Methods and systems for processing read-modify-write requests
A memory system comprises a plurality of memory sub-systems, each with a memory bank and other circuit components. For each of the memory sub-systems, a first buffer receives and stores a read-modify-write request (with a read address, a write address and a first operand), a second operand is read from the memory bank at the location specified by the read address, a combiner circuit combines the first operand with the second operand, an activation circuit transforms the output of the combiner circuit, and the output of the activation circuit is stored in the memory bank at the location specified by the write address. The first operand and the write address may be stored in a second buffer while the second operand is read from the memory bank. Further, the output of the activation circuit may be first stored in the first buffer before being stored in the memory bank.
1. A memory system, comprising:
a memory bank;
a first buffer for storing a read-modify-write request comprising a read address, a write address and a first operand, the first buffer including a write address output, a read address output and a data output;
a second buffer for storing the write address and the first operand, wherein a first input of the second buffer is connected to the write address output of the first buffer, and a second input of the second buffer is connected to the data output of the first buffer;
a combiner circuit for computing intermediary data based on the first operand stored at the second buffer and a second operand read from a first location of the memory bank as specified by the read address;
an activation function circuit for computing activation data based on the intermediary data, wherein the write address specifies a second location in the memory bank where the activation data is written;
a first multiplexor, wherein a first input of the first multiplexor is connected to the data output of the first buffer and a second input of the first multiplexor is connected to an output of the activation function circuit; and
a second multiplexor, wherein a first input of the second multiplexor is connected to a write address output of the second buffer, a second input of the second multiplexor is connected to the write address output of the first buffer, and a third input of the second multiplexor is connected to a read address output of the first buffer.
2. The memory system of claim 1 , wherein the activation data is stored in the memory bank without previously being written to the first or second buffer.
3. The memory system of claim 1 , wherein the write address and the first operand are transmitted from the first buffer to the second buffer.
4. The memory system of claim 1 , wherein the first multiplexor is configured to pass a vector of values from either the first input of the first multiplexor or the second input of the first multiplexor to the memory bank.
5. The memory system of claim 1 , wherein the second multiplexor is configured to pass an address from one of the first, second or third input of the second multiplexor to the memory bank.
6. The memory system of claim 1 , wherein the read address is distinct from the write address.
7. A method, comprising:
storing, at a first buffer, a read-modify-write request comprising a read address, a write address and a first operand;
storing, at a second buffer, the write address and the first operand;
transmitting the read address from the first buffer to a memory bank via a first multiplexor;
reading a second operand from a first location within the memory bank as specified by the read address;
computing, by a combiner circuit, intermediary data based on the first operand stored at the second buffer and the second operand read from the first location within the memory bank; computing, by an activation function circuit, activation data based on the intermediary data;
transmitting the activation data from the activation function circuit to the memory bank via a second multiplexor;
transmitting the write address from the second buffer to the memory bank via the first multiplexor; and
storing the activation data at a second location within the memory bank as specified by the write address.
8. The method of claim 7 , wherein the activation data is stored in the memory bank without previously being written to the first or second buffer.
9. The method of claim 7 , further comprising transmitting the write address and the first operand from the first buffer to the second buffer.
10. The method of claim 7 , further comprising prior to computing the intermediary data at the combiner circuit, transmitting the first operand from the second buffer to the combiner circuit.
11. A memory system, comprising:
a memory bank;
a first buffer for storing a read-modify-write request comprising a read address, a write address and a first operand, the first buffer including a write address output, a read address output and a data output;
a second buffer for storing the write address and the first operand, wherein a first input of the second buffer is connected to the write address output of the first buffer, and a second input of the second buffer is connected to the data output of the first buffer;
a combiner circuit for computing combined data based on the first operand stored at the second buffer and a second operand read from a first location of the memory bank as specified by the read address, wherein the write address specifies a second location in the memory bank where the combined data is written;
a first multiplexor, wherein a first input of the first multiplexor is connected to the data output of the first buffer and a second input of the first multiplexor is connected to an output of the combiner circuit; and
a second multiplexor, wherein a first input of the second multiplexor is connected to a write address output of the second buffer, a second input of the second multiplexor is connected to the write address output of the first buffer, and a third input of the second multiplexor is connected to a read address output of the first buffer.
12. The memory system of claim 11 , wherein the combined data is stored in the memory bank without previously being written to the first or second buffer.
13. The memory system of claim 11 , wherein the write address and the first operand are transmitted from the first buffer to the second buffer.
14. The memory system of claim 11 , wherein the first multiplexor is configured to pass a vector of values from either the first input of the first multiplexor or the second input of the first multiplexor to the memory bank.
15. The memory system of claim 11 , wherein the second multiplexor is configured to pass an address from one of the first, second or third input of the second multiplexor to the memory bank.
16. The memory system of claim 11 , wherein the read address is distinct from the write address.
17. A method, comprising:
storing, at a first buffer, a read-modify-write request comprising a read address, a write address and a first operand;
storing, at a second buffer, the write address and the first operand;
transmitting the read address from the first buffer to a memory bank via a first multiplexor;
reading a second operand from a first location within the memory bank as specified by the read address;
computing, by a combiner circuit, combined data based on the first operand stored at the second buffer and the second operand read from the first location within the memory bank;
transmitting the combined data from the combiner circuit to the memory bank via a second multiplexor;
transmitting the write address from the second buffer to the memory bank via the first multiplexor; and
storing the combined data at a second location within the memory bank as specified by the write address.
18. The method of claim 17 , wherein the combined data is stored in the memory bank without previously being written to the first or second buffer.
19. The method of claim 17 , further comprising transmitting the write address and the first operand from the first buffer to the second buffer.
20. The method of claim 17 , further comprising prior to computing the combined data at the combiner circuit, transmitting the first operand from the second buffer to the combiner circuit.