Apparatus, system, and method for boosting internal voltages of power supply units to extend hold-up times
A disclosed apparatus may boost internal voltages of power supply units (PSUs) to extend hold-up times. For example, an apparatus may include a PSU and a controller. In one example, the PSU may be configured to convert power from an AC input into a direct current (DC) output and provide the DC output to a computing device. In this example, the controller may be configured to detect a loss of the AC input and extend a hold-up time of the PSU in response to detecting the loss of the AC input by modifying at least one switch included in the PSU. Various other apparatuses, systems, and methods are also disclosed.
1. An apparatus comprising:
a power supply unit (PSU) that comprises:
a first switch electrically coupled between a first node and a second node;
a second switch electrically coupled between a third node and a fourth node;
a third switch electrically coupled between the third node and a fifth node;
a first capacitor electrically coupled between the first node and the third node;
a second capacitor electrically coupled between the second node and the fourth node; and
a third capacitor electrically coupled between the fourth node and the fifth node, wherein:
the PSU is configured to:
convert power from an alternating current (AC) input into a direct current (DC) output; and
provide the DC output to a computing device;
the first node comprises a power rail configured to deliver electric current from the first capacitor and the second capacitor to a pulse-width modulation (PWM) stage of the PSU;
the third node comprises a variable node configured to be selectively shorted to an electrical ground when the second switch is opened and the third switch is closed;
the fourth node comprises a branching node configured to provide electric current from the third capacitor to the PWM stage via the first capacitor and the second capacitor when the second switch is closed and the third switch is opened; and
the fifth node comprises the electrical ground; and
circuitry configured to:
detect a loss of the AC input; and
in response to detecting the loss of the AC input, extend a hold-up time of the PSU by modifying an operational state of at least one switch included in the PSU.
2. The apparatus of claim 1 , wherein:
the PSU is further configured to output, to the circuitry, an undervoltage lockout (UVLO) signal that indicates whether the PSU is able to provide a sufficient amount of power to sustain the computing device; and
the circuitry is further configured to detect the loss of the AC input based at least in part on the UVLO signal.
3. The apparatus of claim 1 , wherein the first switch comprises a transistor with a body diode that prevents passage of electric current from the first node to the second node when the transistor is deactivated.
4. The apparatus of claim 1 , wherein the circuitry is further configured to modify the operational state of the at least one switch to boost a voltage level of the power rail.
5. The apparatus of claim 4 , wherein the circuitry is further configured to boost the voltage level of the power rail by at least twenty-five percent.
6. The apparatus of claim 4 , wherein the circuitry is further configured to boost the voltage level of the power rail in response to detecting the loss of the AC input by:
opening the third switch;
opening the first switch after the third switch is opened; and
closing the second switch after the first switch is opened.
7. The apparatus of claim 1 , wherein the at least one switch comprises a transistor whose gate is electrically coupled to the circuitry.
8. The apparatus of claim 1 , wherein the circuitry is further configured to extend the hold-up time of the PSU by at least fifteen percent.
9. A system comprising:
a computing device;
a power supply unit (PSU) that comprises:
a first switch electrically coupled between a first node and a second node;
a second switch electrically coupled between a third node and a fourth node;
a third switch electrically coupled between the third node and a fifth node;
a first capacitor electrically coupled between the first node and the third node;
a second capacitor electrically coupled between the second node and the fourth node; and
a third capacitor electrically coupled between the fourth node and the fifth node, wherein:
the PSU is configured to:
convert power from an alternating current (AC) input into a direct current (DC) output; and
provide the DC output to a computing device;
the first node comprises a power rail configured to deliver electric current from the first capacitor and the second capacitor to a pulse-width modulation (PWM) stage of the PSU;
the third node comprises a variable node configured to be selectively shorted to an electrical ground when the second switch is opened and the third switch is closed;
the fourth node comprises a branching node configured to provide electric current from the third capacitor to the PWM stage via the first capacitor and the second capacitor when the second switch is closed and the third switch is opened; and
the fifth node comprises the electrical ground; and
circuitry configured to:
detect a loss of the AC input; and
in response to detecting the loss of the AC input, extend a hold-up time of the PSU by modifying an operational state of at least one switch included in the PSU.
10. The system of claim 9 , wherein:
the PSU is further configured to output, to the circuitry, an undervoltage lockout (UVLO) signal that indicates whether the PSU is able to provide a sufficient amount of power to sustain the computing device; and
the circuitry is further configured to detect the loss of the AC input based at least in part on the UVLO signal.
11. The system of claim 9 , wherein the first switch comprises a transistor with a body diode that prevents passage of electric current from the first node to the second node when the transistor is deactivated.
12. The system of claim 9 , wherein the circuitry is further configured to modify the operational state of the at least one switch to boost a voltage level of the power rail.
13. The system of claim 12 , wherein the circuitry is further configured to boost the voltage level of the power rail by at least twenty-five percent.
14. A method comprising:
detecting, by circuitry, a loss of an alternating current (AC) input electrically coupled to a power supply unit (PSU) configured to provide a direct current (DC) output to a computing device, wherein:
the PSU comprises:
a first switch electrically coupled between a first node and a second node;
a second switch electrically coupled between a third node and a fourth node;
a third switch electrically coupled between the third node and a fifth node;
a first capacitor electrically coupled between the first node and the third node;
a second capacitor electrically coupled between the second node and the fourth node; and
a third capacitor electrically coupled between the fourth node and the fifth node;
the first node comprises a power rail configured to deliver electric current from the first capacitor and the second capacitor to a pulse-width modulation (PWM) stage of the PSU;
the third node comprises a variable node configured to be selectively shorted to an electrical ground when the second switch is opened and the third switch is closed;
the fourth node comprises a branching node configured to provide electric current from the third capacitor to the PWM stage via the first capacitor and the second capacitor when the second switch is closed and the third switch is opened; and
the fifth node comprises the electrical ground; and
in response to detecting the loss of the AC input:
modifying, by the circuitry, an operational state of at least one switch included in the PSU; and
boosting, as a result of the operational state being modified, a power rail within the PSU to extend a hold-up time of the PSU.