Voltage fluctuation detection circuit
A voltage fluctuation detection circuit includes: a source voltage decrease detection circuit configured to detect a decrease in voltage of a first power supply which outputs a first voltage and to output the result of detection as a voltage decrease detection signal using a second voltage which is lower than the voltage of the first power supply; an erroneous detection prevention circuit configured to detect an increase in voltage of the first power supply and to output the result of detection as a voltage increase detection signal using the second voltage; and a transistor configured to mask outputting of the voltage decrease detection signal in a period in which the increase in voltage of the first power supply is being detected based on the voltage increase detection signal.
1. A voltage fluctuation detection circuit comprising:
a source voltage decrease detection circuit configured to detect a decrease in voltage of a first power supply which outputs a first voltage and to output a result of detection as a voltage decrease detection signal using a second voltage of a second power supply which is lower than the voltage of the first power supply;
an erroneous detection prevention circuit configured to detect an increase in voltage of the first power supply and to output a result of detection as a voltage increase detection signal using the second voltage; and
a mask circuit configured to invalidate outputting of the voltage decrease detection signal in a period in which the increase in voltage of the first power supply is being detected based on the voltage increase detection signal.
2. The voltage fluctuation detection circuit according to claim 1 , wherein the mask circuit includes a first transistor of which a gate is connected to the erroneous detection prevention circuit, a drain is connected to the source voltage decrease detection circuit, and a source is connected to a third power supply.
3. The voltage fluctuation detection circuit according to claim 1 , wherein the source voltage decrease detection circuit includes:
a second transistor of which a source and a back-gate are connected to the first power supply and a gate and a drain are connected to each other;
a third transistor of which a gate is connected to a connection point between the gate and the drain of the second transistor, a source is connected to the first power supply, a drain is connected to an input port of an inverter and a first clamp circuit, and a back-gate is connected to a second clamp circuit and to the first power supply via a first resistor; and
the inverter which is driven with the second power supply and outputs the voltage decrease detection signal.
4. The voltage fluctuation detection circuit according to claim 3 , wherein the second clamp circuit clamps a voltage of the back-gate of the third transistor such that the voltage of the back-gate of the third transistor does not deviate from the voltage of the first power supply by a predetermined voltage or more, and
wherein the first clamp circuit clamps an input voltage of the inverter such that the input voltage of the inverter does not deviate from a voltage of a third power supply by a predetermined voltage or more.
5. The voltage fluctuation detection circuit according to claim 1 , wherein the erroneous detection prevention circuit includes:
a fourth transistor of which a source and a back-gate are connected to the first power supply and a gate and a drain are connected to each other; and
a fifth transistor of which a gate is connected to a connection point between the gate and the drain of the fourth transistor, a source is connected to the first power supply, a drain is connected to a gate of a transistor via a first capacitor, and a back-gate is connected to a third clamp circuit and to the first power supply via a second resistor,
wherein the third clamp circuit includes a sixth transistor of which a gate and a drain are connected to each other, a source and a bulk are connected to each other, and a connection point between the source and the bulk is connected to the gate of the fourth transistor and the gate of the fifth transistor.
6. The voltage fluctuation detection circuit according to claim 5 , wherein the third clamp circuit clamps a voltage of the back-gate of the fifth transistor such that the voltage of the back-gate of the fifth transistor does not deviate from the voltage of the first power supply by a predetermined voltage or more.
7. The voltage fluctuation detection circuit according to claim 1 , wherein the source voltage decrease detection circuit includes:
a third resistor of which a first terminal is connected to the first power supply and a second terminal is connected to a first terminal of a fourth resistor and a first terminal of a third capacitor;
the fourth resistor of which a second terminal is connected to a third power supply;
the third capacitor of which a second terminal is connected to a gate of a seventh transistor; and
the seventh transistor of which a source terminal is connected to the second power supply and a drain terminal outputs the voltage decrease detection signal.
8. The voltage fluctuation detection circuit according to claim 1 , wherein the erroneous detection prevention circuit includes:
a fifth resistor of which a first terminal is connected to the first power supply and a second terminal is connected to a first terminal of a sixth resistor and a first terminal of a fifth capacitor;
the sixth resistor of which a second terminal is connected to a third power supply;
the fifth capacitor of which a second terminal is connected to a gate of an eighth transistor; and
the eighth transistor of which a drain terminal is connected to an input port of an inverter and a source terminal is connected to the third power supply.