Slew rate adjusting circuit for adjusting slew rate, buffer circuit including same, and slew rate adjusting method

1. A slew rate adjusting circuit, comprising:

an adjustment transistor configured to provide an adjustment current into an output port of an arithmetic amplifier in response to the adjustment transistor being turned on;

a first transistor connected between a power line of the arithmetic amplifier and the adjustment transistor;

a second transistor connected between the first transistor and an output node of the output port; and

an enable transistor connected to the adjustment transistor, the first transistor, and the second transistor,

wherein the enable transistor is configured to control whether or not the second transistor is turned on upon receiving an enable signal, and

wherein the adjustment transistor is configured to be turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage.

2. The slew rate adjusting circuit of claim 1 , wherein the adjustment current is provided from the power line into the output node through the adjustment transistor.

3. The slew rate adjusting circuit of claim 1 ,

wherein the second transistor is configured to be turned on in response to the difference between the input voltage and the output voltage being equal to or greater than the reference voltage, and

wherein the adjustment transistor is configured to be turned on in response to the second transistor being turned on, and the adjustment current is provided to the output node through the adjustment transistor in response to the adjustment transistor being turned on.

4. The slew rate adjusting circuit of claim 1 ,

wherein the adjustment transistor, the first transistor, and the second transistor are metal-oxide-semiconductor field-effect transistors (MOSFETs), and

wherein a source terminal of the second transistor is connected to the output node, a drain terminal of the second transistor is connected to a gate terminal of the adjustment transistor, a source terminal of the adjustment transistor is connected to the power line, and a drain terminal of the adjustment transistor is connected to the output node.

5. The slew rate adjusting circuit of claim 1 ,

wherein the adjustment transistor and the second transistor are metal-oxide-semiconductor field-effect transistors (MOSFETs), and

wherein a source terminal of the second transistor is connected to the output node, a drain terminal of the second transistor is connected to a gate terminal of the adjustment transistor, a source terminal of the adjustment transistor is connected to the power line, and a drain terminal of the adjustment transistor is connected to the output node.

6. The slew rate adjusting circuit of claim 1 , wherein a positive adjustment current is provided through the adjustment transistor in response to the arithmetic amplifier operating through a pull-up current.

7. The slew rate adjusting circuit of claim 1 , wherein a negative adjustment current is provided through the adjustment transistor in response to the arithmetic amplifier operating through a pull-down current.

8. The slew rate adjusting circuit of claim 1 , further comprising an additional transistor connected to the adjustment transistor, the first transistor, and the second transistor,

wherein the second transistor is configured to turn on the additional transistor in response to the difference between the input voltage and the output voltage being equal to or greater than the reference voltage, and

wherein an additional current is provided to the output node in response to the additional transistor being turned on.