Integrated circuit with address remapping circuitry to respond to a memory access request
A system on chip (SoC) includes a CPU, a main bus, and a plurality of subsystems. The SoC also includes an address remapping module coupled between the CPU and the bus. The address remapping module quickly and efficiently changes any memory addresses that need to be changed with the CPU requests a read or write operation associated with the addresses.
1. A device, comprising:
a CPU;
a bus;
a sub-system coupled to the bus;
address remapping circuitry coupled between the CPU and the bus; and
a system register coupled to the address remapping circuitry, wherein:
the CPU, in operation, provides a memory access request to the address remapping circuitry to access a memory of the sub-system via the bus,
the memory access request includes a requested memory address, wherein the address remapping circuitry, in operation, receives address matching data and address adjustment data from the system register,
the memory access request includes a data size, wherein the address remapping circuitry, in operation, provides the data size and an update address request to the system register, and
the system register, in operation, provides the address matching data and the address adjustment data to the address remapping circuitry in response to the update address request.
2. The device of claim 1 , wherein the address remapping circuitry includes a comparison circuit, which, in operation, compares the requested memory address to the address matching data.
3. The device of claim 2 , wherein if the requested memory address does not match any address from the address matching data then the address remapping circuitry, in operation, provides the requested memory address to the bus, wherein if the requested memory address matches an address from the address matching data then the address remapping circuitry, in operation, provides an adjusted memory address from the address adjustment data to the bus.
4. The device of claim 1 , wherein the address remapping circuitry includes a logic circuit.
5. The device of claim 1 , wherein the system register, in operation, stores the address matching data, the address adjustment data, a start address associated with the memory, an end address associated with the memory, a buffer size associated with the memory, and a stride associated with the address adjustment data.
6. The device of claim 5 , wherein the address matching data includes a plurality of memory address associated with the memory, wherein the address adjustment data includes a plurality of adjusted addresses each associated with one of the memory addresses of the address matching data.
7. The device of claim 1 , wherein the system register includes a plurality of sub-registers each associated with a respective memory and including address matching data and address adjustment data associated with the respective memory.
8. The device of claim 1 , wherein the memory access request corresponds to reading data from the memory to the CPU.
9. The device of claim 1 , wherein the memory access request corresponds to writing data to the memory the CPU.
10. A method, comprising:
providing, from a CPU to an address remapping circuit coupled between the CPU and a bus, a memory access request including a requested memory address for accessing a memory of a sub-system coupled to the bus;
comparing, with the address remapping circuit, the requested memory address to address matching data including a plurality of addresses;
in response to the requested memory address not matching any of the plurality of addresses of the address matching data, providing the requested memory address to the bus from the address remapping circuit; and
in response to the requested memory address matching an address from the address matching data, retrieving an adjusted memory address from address adjustment data associated with the address matching data and providing the adjusted memory address to the bus from the address remapping circuit, wherein the method comprises:
providing, from the address remapping circuit to a system register, an update request responsive to receiving the memory access request; and
receiving, with the address remapping circuit, the address matching data and the address adjustment data from the system register responsive to the update request.
11. The method of claim 10 , wherein the update request includes a data size associated with the memory access request.
12. A system, comprising:
a processor;
a bus;
a sub-system coupled to the bus;
a system register; and
address remapping circuitry coupled to the system register, the processor and the bus, wherein the address remapping circuitry, in response to a memory access request received from the processor to access a memory of the sub-system:
compares a memory address of the memory access request to address matching data including a plurality of memory addresses;
in response to the memory address of the memory access request not matching any of the plurality of memory addresses of the address matching data, provides the requested memory address to the bus; and
in response to the memory address of the memory access request matching an address of the plurality of memory addresses of the address matching data, retrieves an adjusted memory address from address adjustment data associated with the address matching data and provides the adjusted memory address to the bus, wherein,
the system register, in operation, stores a start address associated with the memory, an end address associated with the memory, a buffer size associated with the memory, and a stride associated with the address adjustment data.
13. The system of claim 12 , wherein the system register, in operation, stores the address matching data and the address adjustment data.
14. The system of claim 12 , wherein the address remapping circuitry includes a comparison circuit, which, in operation, compares the memory address of the memory access request to the address matching data.
15. The system of claim 12 , wherein the system register includes a plurality of sub-registers each associated with a respective memory and including address matching data and address adjustment data associated with the respective memory.