Memory chip and memory system including the same
A memory chip includes a plurality of storage blocks respectively including a plurality of memory cells; and a logic circuit configured to control the plurality of storage blocks, wherein the logic circuit includes an input/output pad configured to input data to the plurality of storage blocks and output data to the plurality of storage blocks; wherein the logic circuit is further configured to allocate block address codes having a bit inversion relationship with each other, output a mode selection signal in response to external control, output an external address code in response to the mode selection signal indicating a first addressing mode, and output an address code having a bit inversion relationship with regard to the external address code in response to the mode selection signal indicating a second addressing mode, and select a storage block to be controlled by the access command from among the plurality of storage blocks.
1. A memory chip comprising:
a plurality of storage blocks respectively including a plurality of memory cells; and
a logic circuit configured to control the plurality of storage blocks,
wherein the logic circuit includes
an input/output pad configured to input data to the plurality of storage blocks and output data to the plurality of storage blocks, wherein the logic circuit is further configured to
allocate block address codes having a bit inversion relationship with each other, to a storage block having a k th longest distance from the input/output pad among the plurality of storage blocks and a storage block having a k th shortest distance from the input/output pad among the plurality of storage blocks, where k is a natural number, among the plurality of storage blocks,
output a mode selection signal in response to external control,
output an external address code received together with an access command in response to the mode selection signal indicating a first addressing mode, and output a first address code having the bit inversion relationship with regard to the external address code in response to the mode selection signal indicating a second addressing mode, and
select a first storage block to be controlled by the access command from among the plurality of storage blocks, based on the external address code or the first address code.
2. The memory chip of claim 1 , wherein the bit inversion relationship is a relationship in which at least one bit of each of the block address codes is inverted.
3. The memory chip of claim 2 , wherein a number of storage blocks in the plurality of storage blocks is 2 N , where N is a natural number,
each of the block address codes is an N-bit code, and
the logic circuit is configured to allocate a block address code having a larger code value to a storage block among the plurality of storage blocks, as a distance between the storage block and the input/output pad increases.
4. The memory chip of claim 1 , wherein
the logic circuit further comprises a mode register and a fuse circuit, the mode register including a value, the mode register configured to set the value in response to the external control, and
the logic circuit is configured to output the mode selection signal, based on an XOR operation result of a value of the mode register and an output value of the fuse circuit.
5. The memory chip of claim 4 , wherein the logic circuit is configured to output the mode selection signal, based on an OR operation result of the value of the mode register and the output value of the fuse circuit.
6. The memory chip of claim 1 , wherein the plurality of storage blocks are arranged in a line on a side of the input/output pad.
7. The memory chip of claim 1 , wherein the plurality of storage blocks are arranged on opposing sides of the input/output pad.
8. The memory chip of claim 1 , wherein each of the plurality of storage blocks comprises:
a row decoder configured to select a row address of the plurality of memory cells; and
a column decoder configured to select a column address of the plurality of memory cells,
wherein each of the plurality of storage blocks is configured to perform respective access operations in parallel.