IP Library Granted Patent US 12,034,579
Granted Patent B2
US 12,034,579 · App. 18/193,241 · Granted Jul 9, 2024

Apparatus, system and method of transmitting a PPDU

Inventors: Alexander Maltsev (Nizhny Novgorod, RU); Carlos Cordeiro (Portland, OR); Artyom Lomayev (Nizhny Novgorod, RU); Michael Genossar (Modiin, IL); Claudio Da Silva (Portland, OR)
Assignee: INTEL CORPORATION
H04L27/2613H03M13/11H04J13/0014H04L1/0061H04L27/2605
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Quick Facts
Patent No.
US 12,034,579
App. No.
18/193,241
Granted
Jul 9, 2024
Kind
B2
Abstract

An apparatus of a transmitter may include, for example, a Golay builder to build modulated Golay sequences for at least a non-EDMG Short Training Field (L-STF), and a non-EDMG Channel Estimation Field (L-CEF) of a PPDU; a scrambler to generate scrambled bits by scrambling bits of a non-EDMG header (L-header) and a data field of the PPDU; an encoder to encode the scrambled bits into encoded bits according to a low-density parity-check (LDPC) code; a constellation mapper to map the encoded bits into a stream of constellation points according to a constellation scheme; a spreader to spread the stream of constellation points according to a Golay sequence; and a transmit chain mapper to map a bit stream output from the Golay builder and the spreader to a plurality of transmit chains by applying a spatial expansion with relative cyclic shift over the plurality of transmit chains.

Claims (36)

1. An apparatus comprising:

transmitter circuitry configured to generate a transmission of an Enhanced Directional Multi-Gigabit (DMG) (EDMG) Physical layer (PHY) Protocol Data Unit (PPDU), the transmitter circuitry comprising:

Golay builder circuitry to build modulated Golay sequences of a non-EDMG Short Training Field (L-STF) and a non-EDMG Channel Estimation Field (L-CEF) of the EDMG PPDU;

scrambler circuitry to generate scrambled bits by scrambling bits of a non-EDMG header (L-header) and an EDMG Header A of the EDMG PPDU;

Low-Density Parity-Check (LDPC) encoder circuitry to encode the scrambled bits into encoded bits according to an LDPC code;

constellation mapper circuitry to map the encoded bits into constellation points; and

spatial mapper circuitry configured to map a pre-EDMG stream to a plurality of transmit chains by applying a relative cyclic shift over the plurality of transmit chains, wherein the pre-EDMG stream comprises the constellation points from the constellation mapper circuitry and the modulated Golay sequences of the L-STF and the L-CEF from the Golay builder circuitry.

2. The apparatus of claim 1 , wherein the spatial mapper circuitry is configured to map one or more EDMG streams to the plurality of transmit chains, the one or more EDMG streams based on a data field of the EDMG PPDU.

3. The apparatus of claim 2 , wherein the one or more EDMG streams comprises a plurality of space-time streams based on the data field of the EDMG PPDU.

4. The apparatus of claim 1 comprising combiner circuitry to provide the pre-EDMG stream by combining the modulated Golay sequences of the L-STF and L-CEF from the Golay builder circuitry with the constellation points from the constellation mapper circuitry.

5. The apparatus of claim 1 , wherein the L-STF, the L-CEF and the L-Header are configured for decoding by non-EDMG Stations (STAs), which are DMG STAs, and wherein the EDMG Header A is configured for decoding by EDMG STAs.

6. The apparatus of claim 1 , wherein the Golay builder circuitry is configured to build the modulated Golay sequences comprising π/2 Binary Phase Shift Keying (BPSK) modulated Golay sequences.

7. The apparatus of claim 1 comprising pulse shaper circuitry configured to perform over the plurality of transmit chains convolution of constellation points with a shape filter impulse response.

8. The apparatus of claim 7 , wherein the pulse shaper circuitry is configured to perform pulse shaping with a relative time delay between a primary channel and a secondary channel for a duplicate transmission.

9. The apparatus of claim 1 , wherein the transmitter circuitry is configured to duplicate transmission of the L-STF, the L-CEF, the L-Header and the EDMG Header A over a plurality of 2.16 Gigahertz (GHz) channels in a channel bandwidth of at least 4.32 GHz.

10. The apparatus of claim 1 , wherein the transmitter circuitry is configured to generate the transmission of the EDMG PPDU in a channel bandwidth of at least 2.16 Gigahertz (GHz) over a frequency band above 45 GHz.

11. The apparatus of claim 10 , wherein the transmitter circuitry is configured to generate the transmission of the EDMG PPDU over a channel bandwidth of 4.32 GHz, 6.48 GHz, or 8.64 GHz.

12. The apparatus of claim 1 comprising the plurality of transmit chains to transmit the EDMG PPDU.

13. The apparatus of claim 12 comprising a plurality of antennas connected to the plurality of transmit chains, a memory, and a processor to execute instructions of an Operating System (OS).

14. A product comprising one or more tangible computer-readable non-transitory storage media comprising instructions operable to, when executed by at least one processor, enable the at least one processor to cause an Enhanced Directional Multi-Gigabit (DMG) (EDMG) transmitter to:

build modulated Golay sequences of a non-EDMG Short Training Field (L-STF) and a non-EDMG Channel Estimation Field (L-CEF) of an EDMG Physical layer (PHY) Protocol Data Unit (PPDU);

generate scrambled bits by scrambling bits of a non-EDMG header (L-header) and an EDMG Header A of the EDMG PPDU;

encode the scrambled bits into encoded bits according to a Low-Density Parity-Check (LDPC) code;

map the encoded bits into constellation points; and

map a pre-EDMG stream to a plurality of transmit chains by applying a relative cyclic shift over the plurality of transmit chains, wherein the pre-EDMG stream comprises the encoded bits mapped to the constellation points and the modulated Golay sequences of the L-STF and the L-CEF.

15. The product of claim 14 , wherein the instructions, when executed, cause the EDMG transmitter to map one or more EDMG streams to the plurality of transmit chains, the one or more EDMG streams based on a data field of the EDMG PPDU.

16. The product of claim 14 , wherein the instructions, when executed, cause the EDMG transmitter to perform over the plurality of transmit chains convolution of constellation points with a shape filter impulse response.

17. The product of claim 14 , wherein the instructions, when executed, cause the EDMG transmitter to duplicate transmission of the L-STF, the L-CEF, the L-Header and the EDMG Header A over a plurality of 2.16 Gigahertz (GHz) channels in a channel bandwidth of at least 4.32 GHz.

18. The product of claim 14 , wherein the instructions, when executed, cause the EDMG transmitter to transmit the EDMG PPDU in a channel bandwidth of at least 2.16 Gigahertz (GHz) over a frequency band above 45 GHz.

19. An apparatus for an Enhanced Directional Multi-Gigabit (DMG) (EDMG) transmitter, the apparatus comprising:

means for building modulated Golay sequences of a non-EDMG Short Training Field (L-STF) and a non-EDMG Channel Estimation Field (L-CEF) of an EDMG Physical layer (PHY) Protocol Data Unit (PPDU);

means for generating scrambled bits by scrambling bits of a non-EDMG header (L-header) and an EDMG Header A of the EDMG PPDU;

means for encoding the scrambled bits into encoded bits according to a Low-Density Parity-Check (LDPC) code;

means for mapping the encoded bits into constellation points; and

means for mapping a pre-EDMG stream to a plurality of transmit chains by applying a relative cyclic shift over the plurality of transmit chains, wherein the pre-EDMG stream comprises the encoded bits mapped to the constellation points and the modulated Golay sequences of the L-STF and the L-CEF.

20. The apparatus of claim 19 comprising means for mapping one or more EDMG streams to the plurality of transmit chains, the one or more EDMG streams based on a data field of the EDMG PPDU.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2023
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 063815/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2023
From: MALTSEV, ALEXANDER; CORDEIRO, CARLOS; LOMAYEV, ARTYOM; GENOSSAR, MICHAEL; DA SILVA, CLAUDIO
To: INTEL IP CORPORATION
Reel/Frame 063475/0633 →
Continuity (8)
Continuation 17483442 · Sep 23, 2021
Continuation 17346951 · Jun 14, 2021
Continuation 16907244 · Jun 21, 2020
Continuation 16626463
Provisional Application 62576473 · Oct 24, 2017
Provisional Application 62547982 · Aug 21, 2017
Provisional Application 62524552 · Jun 25, 2017
Related Publication 20230246894A1 · Aug 3, 2023