Operating a voltage regulator at peak efficiency
View Patent ↗Methods, systems, and products for operating a VRD at peak efficiency includes: generating, during operation of a computing system that includes a VRD providing power to a processor, an efficiency histogram for the VRD, identifying, from the efficiency histogram, a power output level associated with the VRD operating at peak power efficiency, and setting a power cap for the processor at the power output level.
1 . A method of controlling voltage regulator efficiency, the method comprising:
generating, during operation of a computing system that includes a VRD (voltage regulator device) providing power to a processor, an efficiency histogram for the VRD;
identifying, from the efficiency histogram, a power output level associated with the VRD operating at peak power efficiency; and
setting a power cap for the processor at the power output level.
2 . The method of claim 1 , wherein setting the power cap for the processor includes setting, for the processor, a maximum allowed P-state associated with the power output level.
3 . The method of claim 2 , wherein the maximum allowed P-state is less than a maximum P-state supported by the processor.
4 . The method of claim 2 , wherein the processor, during execution, operates at a plurality of P-states without exceeding the maximum allowed P-state.
5 . The method of claim 2 , further comprising:
instructing the processor to, when active, skip to the maximum allowed P-state.
6 . The method of claim 5 , wherein instructing the processor to skip to the maximum allowed P-state further comprises instructing the processor to skip to the maximum allowed P-state based on characteristics of a workload executing on the processor.
7 . The method of claim 1 , wherein the processor comprises a CPU (central processing unit).
8 . The method of claim 1 , wherein the processor comprises a GPU (graphics processing unit).
9 . The method of claim 1 , wherein the processor comprises a hardware accelerator, and wherein the power cap set is specific to the processor.
10 . A system for controlling voltage regulator efficiency, the system comprising:
a processor;
a VRD (voltage regulator device) providing power to the processor; and
a BMC (baseboard management controller) configured to:
generate, during operation of the system, an efficiency histogram for the VRD;
identify, from the efficiency histogram, a power output level associated with the VRD operating at peak power efficiency; and
set a power cap for the processor at the power output level.
11 . The system of claim 10 , wherein setting the power cap for the processor includes setting, for the processor, a maximum allowed P-state associated with the power output level.
12 . The system of claim 11 , wherein the maximum allowed P-state is less than a maximum P-state supported by the processor.
13 . The system of claim 11 , wherein the processor, during execution, operates at a plurality of P-states without exceeding the maximum allowed P-state.
14 . The system of claim 11 , further comprising:
instructing the processor to, when active, skip to the maximum allowed P-state.
15 . The system of claim 14 , wherein instructing the processor to skip to the maximum allowed P-state further comprises instructing the processor to skip to the maximum allowed P-state based on characteristics of a workload executing on the processor.
16 . The system of claim 10 , wherein the processor comprises a CPU (central processing unit).
17 . A computer program product for controlling voltage regulator efficiency, the computer program product comprising a non-volatile computer readable medium and computer program instructions stored therein that are configured to, when executed, cause a computer to perform operations comprising:
generating, during operation of a computing system that includes a VRD (voltage regulator device) providing power to a processor, an efficiency histogram for the VRD;
identifying, from the efficiency histogram, a power output level associated with the VRD operating at peak power efficiency; and
setting a power cap for the processor at the power output level.
18 . The computer program product of claim 17 , wherein setting the power cap for the processor includes setting, for the processor, a maximum allowed P-state associated with the power output level.
19 . The computer program product of claim 18 , further comprising:
instructing the processor to, when active, skip to the maximum allowed P-state.
20 . The computer program product of claim 19 , wherein instructing the processor to skip to the maximum allowed P-state further comprises instructing the processor to skip to the maximum allowed P-state based on characteristics of a workload executing on the processor.