NEURAL NETWORK INCLUDING LOCAL STORAGE UNIT
A neural network includes an internal storage unit. The internal storage unit stores feature data received from a memory external to the neural network. The internal storage unit reads the feature data to a hardware accelerator of the neural network. The internal storage unit adapts a storage pattern of the feature data and a read pattern of the feature data to enhance the efficiency of the hardware accelerator.
1 . A method, comprising:
receiving, at a neural network, feature data from a memory external to the neural network;
passing the feature data to an internal storage of the neural network;
storing, with a write transformation unit of the internal storage, the feature data in the internal storage with a first address configuration based on a first hardware accelerator that is next in a flow of the neural network;
passing the feature data from the internal storage to the first hardware accelerator; and
generating first transformed feature data by processing the feature data with the first hardware accelerator.
2 . The method of claim 1 , comprising passing the first transformed feature data to the memory.
3 . The method of claim 2 , comprising:
receiving, at the neural network, the first transformed feature data from the memory;
passing the first transformed feature data to the internal storage;
storing, with the write transformation unit of the internal storage, the transformed feature data in the internal storage with a second address configuration based on a second hardware accelerator that is next in the flow of the neural network;
passing the transformed feature data from the internal storage to the second hardware accelerator; and
generating second transformed feature data by processing the first transformed feature data with the second hardware accelerator.
4 . The method of claim 1 , wherein the first hardware accelerator is a convolution accelerator.
5 . The method of claim 4 , wherein the first address configuration is based on a kernel size associated with the convolution accelerator.
6 . The method of claim 4 , wherein passing the transformed feature data includes reading, with a read transformation unit the feature data from the internal storage with a read address pattern based on the first hardware accelerator.
7 . The method of claim 6 , wherein the read address patter is based on a kernel size associated with the convolution accelerator.
8 . The method of claim 5 , comprising:
receiving the feature data in rows with the internal storage from the memory; and
reading the data from internal storage in columns with the read transformation unit.
9 . The method of claim 5 , comprising controlling the read transformation unit with a control unit of the internal storage.
10 . The method of claim 1 , comprising controlling the write transformation unit with configuration registers of the neural network.
11 . A method, comprising:
receiving, at a neural network, feature data from a memory external to the neural network;
passing the feature data to an internal storage of the neural network;
storing the feature data in the internal storage;
reading, with a read transformation unit of the neural network, the feature data to a first hardware accelerator with a read address pattern based on an operation of the first hardware accelerator;
generating first transformed feature data by processing the feature data with the first hardware accelerator.
12 . The method of claim 11 , wherein the first hardware accelerator is a convolution accelerator.
13 . The method of claim 12 , wherein the read address pattern is based on a kernel size of the first hardware accelerator.
14 . The method of claim 13 , wherein the feature data is a feature tensor.
15 . The method of claim 11 , comprising:
determining, with a control unit of the internal storage, whether a sufficient amount of the feature data has been received at the internal storage; and
reading the feature data from the internal storage to the first hardware accelerator only if the control unit determines that a sufficient amount of the feature data has been received at the internal storage.
16 . The method of claim 11 , comprising passing the first transformed feature data to the memory.
17 . The method of claim 16 , comprising:
receiving, at the neural network, the first transformed feature data from the memory;
passing the first transformed feature data to the internal storage;
storing, with a write transformation unit of the internal storage, the transformed feature data in the internal storage with an address configuration based on a second hardware accelerator that is next in a flow of the neural network;
passing the first transformed feature data from the internal storage to the second hardware accelerator; and
generating second transformed feature data by processing the first transformed feature data with the second hardware accelerator.
18 . A device comprising a neural network, the neural network including:
a stream engine configured to receive feature data from a memory external to the neural network;
a hardware accelerator; and
an internal storage configured to receive the feature data from the stream engine, the internal storage including:
a write transformation unit configured to write the feature data into the internal storage with a write address pattern based on a configuration of the hardware accelerator; and
a read transformation unit configured to read the feature data to the hardware accelerator with a read address pattern based on the configuration of the hardware accelerator, the hardware accelerator configured to receive the feature data from the internal storage and to process the feature data to generate transformed feature data.
19 . The device of claim 18 , wherein the internal storage includes a control unit configured to control the read transformation unit.
20 . The device of claim 18 , wherein the neural network is a convolutional neural network.