EMITTER ASSEMBLY WITH VERTICAL CAVITY SURFACE EMITTING LASER (VCSEL) CLUSTERS

1 . An emitter assembly, comprising:

a vertical cavity surface emitting laser (VCSEL) chip comprising a plurality of VCSELs in a bottom-emitting configuration,

wherein multiple VCSELs, of the plurality of VCSELs, are grouped in a cluster; a carrier,

wherein the VCSEL chip is in a flip chip configuration with the carrier; and

a conductive pillar electrically connected to the multiple VCSELs grouped in the cluster.

2 . The emitter assembly of claim 1 , wherein the carrier comprises an integrated circuit chip or a substrate.

3 . The emitter assembly of claim 1 , wherein the carrier comprises a surface layer and a base layer, and

wherein the surface layer comprises a redistribution layer.

4 . The emitter assembly of claim 1 , wherein the conductive pillar has a solder cap at an end of the conductive pillar, and

wherein the solder cap surrounds the multiple VCSELs.

5 . The emitter assembly of claim 1 , wherein the conductive pillar has a solder cap at an end of the conductive pillar, and

wherein the solder cap is electrically connected to the multiple VCSELs.

6 . The emitter assembly of claim 1 , wherein the conductive pillar electrically connects the cluster of the multiple VCSELs and the carrier.

7 . The emitter assembly of claim 1 , wherein the conductive pillar extends from the VCSEL chip to the carrier.

8 . The emitter assembly of claim 1 , wherein the conductive pillar extends from the carrier to the VCSEL chip.

9 . The emitter assembly of claim 1 , further comprising:

underfill between the VCSEL chip and the carrier.

10 . The emitter assembly of claim 9 , wherein the carrier comprises:

a thermal element aligned with the multiple VCSELs grouped in the cluster,

wherein the thermal element is separated from the VCSEL chip by the underfill.

11 . A vertical cavity surface emitting laser (VCSEL) chip, comprising:

a plurality of VCSELs in a bottom-emitting configuration,

wherein multiple VCSELs, of the plurality of VCSELs, are grouped in a cluster; and

an electrical contact shared by the multiple VCSELs grouped in the cluster,

wherein the electrical contact is electrically connected to the multiple VCSELs, and

wherein the electrical contact is configured to electrically connect to a conductive pillar that provides electrical connection of the VCSEL chip and a carrier.

12 . The VCSEL chip of claim 11 , wherein the multiple VCSELs grouped in the cluster are arranged in a row.

13 . The VCSEL chip of claim 11 , wherein the multiple VCSELs grouped in the cluster are arranged non-linearly.

14 . The VCSEL chip of claim 11 , wherein the electrical contact is outside of a region occupied by the multiple VCSELs grouped in the cluster.

15 . The VCSEL chip of claim 11 , wherein the multiple VCSELs are multiple first VCSELs, the cluster is a first cluster, and the electrical contact is a first electrical contact,

wherein multiple second VCSELs, of the plurality of VCSELs, are grouped in a second cluster, and

wherein the VCSEL chip further comprises:

a second electrical contact, electrically isolated from the first electrical contact, shared by the multiple second VCSELs,

wherein the second electrical contact is electrically connected to the multiple second VCSELs.

16 . The VCSEL chip of claim 11 , wherein a spacing of the plurality of VCSELs defines a pitch that is less than 45 micrometers.

17 . A method, comprising:

assembling a vertical cavity surface emitting laser (VCSEL) chip in a flip chip configuration with a carrier to produce an emitter assembly,

wherein the VCSEL chip comprises a plurality of VCSELs, and multiple VCSELs, of the plurality of VCSELs, are grouped in a cluster that shares an electrical contact, and

wherein a conductive pillar is to electrically connect to the electrical contact of the cluster of the multiple VCSELs; and

performing a solder reflow procedure on the emitter assembly.

18 . The method of claim 17 , wherein the VCSEL chip and the carrier are passively aligned in the solder reflow procedure.

19 . The method of claim 17 , wherein the solder reflow procedure causes electrical connection of the conductive pillar and the electrical contact.

20 . The method of claim 17 , further comprising:

applying solder flux on the carrier prior to assembling the VCSEL chip in the flip chip configuration with the carrier.