Multiple system-on-chip arrangement for vehicle computing systems
A computing system can include a first system on chip (SoC) and a second SoC. Each SoC can comprise a memory in which the SoC publishes state information. For the first SoC, the state information can correspond to a set of tasks being performed by the first SoC, where the first SoC utilizes a plurality of computational components to perform the set of tasks. The first SoC can directly access the memory of the first SoC to dynamically read the state information published by the first SoC. In a backup role, the second SoC maintains a subset of its computational components in a low power state. When the second SoC detects a trigger while reading the state information published in the first memory of the first SoC, the second SoC powers the subset of computational components to take over the set of tasks.
1. A computing system comprising:
a first system on a chip (SoC) comprising a first memory in which the first SoC publishes state information corresponding to a set of tasks being performed by the first SoC, the first SoC comprising a first plurality of computational components; and
a second SoC comprising a second memory and a second plurality of computational components, the second SoC having memory access to the first memory of the first SoC to dynamically read the state information published by the first SoC, wherein the second SoC maintains a subset of the second plurality of computational components in a low power state;
wherein when the second SoC detects a trigger while reading the state information published in the first memory of the first SoC, the second SoC powers the subset of the second plurality of computational components to take over the set of tasks;
wherein each time the computing system is rebooted, the first SoC and the second SoC switch roles in (i) performing the set of tasks versus (ii) placing a subset of their respective plurality of computational components in the low power state and dynamically reading published state information from the first SoC or second SoC.
2. The computing system of claim 1 , wherein the set of tasks comprises autonomous driving tasks.
3. The computing system of claim 2 , wherein the autonomous driving tasks comprise sensor data perception and inference tasks for autonomously operating a vehicle along a travel route.
4. The computing system of claim 1 , wherein the trigger corresponds to the first SoC experiencing a fault or a failure, the fault or the failure corresponding to the first SoC overheating, a power surge, or an error in the first SoC.
5. The computing system of claim 1 , wherein the first SoC is powered by a first power source of a vehicle, and wherein the second SoC is powered by a second power source of the vehicle.
6. The computing system of claim 5 , wherein the first power source comprises a battery pack used for propulsion of the vehicle, and wherein the second power source comprises an auxiliary power source of the vehicle.
7. The computing system of claim 1 , wherein the first SoC and the second SoC are electrically coupled to each other via an interconnect having at least one electrical safety switch to protect the computing system from power surges from either the first SoC or the second SoC.
8. The computing system of claim 1 , wherein the first SoC dynamically reads the second memory of the second SoC to determine whether the second SoC is ready to take over the set of tasks being performed by the first SoC.
9. The computing system of claim 1 , wherein the first SoC and the second SoC being arranged to dynamically read the state information and take over the set of tasks provides redundancy to facilitate an automotive safety integrity level (ASIL) rating for the computing system.
10. The computing system of claim 1 , wherein the first plurality of computational components and the second plurality of computational components comprise chiplets of each of the first SoC and the second SoC.
11. The computing system of claim 10 , wherein the subset of the second plurality of computational components of the second SoC that are in the low power state comprise a plurality of the following: one or more general compute chiplets, one or more autonomous drive chiplets, one or more machine learning accelerator chiplets, one or more sensor input chiplets, or one or more high bandwidth memory chiplets.
12. The computing system of claim 11 , wherein the first plurality of computational components of the first SoC and the second plurality of computational components of the second SoC each include a functional safety (FuSa) CPU that publishes state information of the first SoC and the second SoC to a FuSa component of the first memory and the second memory respectively.
13. The computing system of claim 12 , wherein the first SoC and the second SoC do not place the FuSa CPU in the low power state.
14. The computing system of claim 1 , wherein when the second SoC takes over the set of tasks from the first SoC, the first SoC resets or reboots the first plurality of computational components.
15. A computing system comprising:
a first system on a chip (SoC) comprising a first memory in which the first SoC publishes state information corresponding to a set of tasks being performed by the first SoC, the first SoC comprising a first plurality of computational components, wherein the state information comprises statistical information corresponding to a surrounding environment of a vehicle in which the computing system resides; and
a second SoC comprising a second memory and a second plurality of computational components, the second SoC having memory access to the first memory of the first SoC to dynamically read the state information published by the first SoC, wherein the second SoC maintains a subset of the second plurality of computational components in a low power state,
wherein when the second SoC detects a trigger while reading the state information published in the first memory of the first SoC, the second SoC powers the subset of the second plurality of computational components to take over the set of tasks.
16. A computer-implemented method comprising:
at a first system on a chip (SoC) comprising a first memory, publishing state information corresponding to a set of tasks being performed by the first SoC in the first memory, the first SoC comprising a first plurality of computational components, wherein the state information comprises statistical information corresponding to a surrounding environment of a vehicle in which the computing system resides; and
at a second SoC comprising a second memory and a second plurality of computational components, ( 1 ) accessing the first memory of the first SoC to dynamically read the state information published by the first SoC, wherein the second SoC maintains a subset of the second plurality of computational components in a low power state, (ii) detecting a trigger while reading the state information published in the first memory of the first SoC, and (iii) in response to detecting the trigger, powering the subset of the second plurality of computational components to take over the set of tasks from the first SoC.
17. The computer-implemented method of claim 16 , wherein the set of tasks comprises autonomous driving tasks.
18. The computer-implemented method of claim 17 , wherein the autonomous driving tasks comprise sensor data perception and inference tasks for autonomously operating a vehicle along a travel route.