IP Library Granted Patent US 12,210,478
Granted Patent B2
US 12,210,478 · App. 18/196,418 · Granted Jan 28, 2025

Overlay layer hardware unit for network of processor cores

Inventors: Ivan Matosevic (Toronto, CA); Davor Capalija (Toronto, CA); Jasmina Vasiljevic (Toronto, CA); Utku Aydonat (Toronto, CA); S. Alexander Chin (Toronto, CA); Djordje Maksimovic (Toronto, CA); Ljubisa Bajic (Toronto, CA)
Assignee: Tenstorrent Inc.
G06F15/7871G06F15/173G06F15/7825G06F15/825G06F9/3004
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Quick Facts
Patent No.
US 12,210,478
App. No.
18/196,418
Granted
Jan 28, 2025
Kind
B2
Abstract

Methods and systems for executing an application data flow graph on a set of computational nodes are disclosed. The computational nodes can each include a programmable controller from a set of programmable controllers, a memory from a set of memories, a network interface unit from a set of network interface units, and an endpoint from a set of endpoints. A disclosed method comprises configuring the programmable controllers with instructions. The method also comprises independently and asynchronously executing the instructions using the set of programmable controllers in response to a set of events exchanged between the programmable controllers themselves, between the programmable controllers and the network interface units, and between the programmable controllers and the set of endpoints. The method also comprises transitioning data in the set of memories on the computational nodes in accordance with the application data flow graph and in response to the execution of the instructions.

Claims (111)

1. A system for executing a complex computation on a set of processing cores, the system comprising:

a set of processing pipelines, wherein each processing core in the set of processing cores includes at least one processing pipeline from the set of processing pipelines;

a set of static random-access memories, wherein each processing core in the set of processing cores includes at least one static random-access memory from the set of static random-access memories;

a set of core controllers to administrate transfers of data from the set of static random-access memories to the set of processing pipelines to execute a set of component computations required for the complex computation, wherein each processing core in the set of processing cores includes at least one core controller from the set of core controllers; and

a set of programmable controllers, wherein the programmable controllers in the set of programmable controllers are programmable stream controllers and are configurable using instructions, wherein the set of programmable controllers execute the instructions to execute an application data flow graph required for the complex computation, and wherein each processing core in the set of processing cores includes at least one programmable controller from the set of programmable controllers;

wherein the application data flow graph requires data for the complex computation to flow between the processing cores in the set of processing cores and the data for the complex computation is streamed between the processing cores in the set of processing cores.

2. The system of claim 1 , wherein:

the set of programmable controllers execute the instructions independently of the set of core controllers.

3. The system of claim 1 , further comprising:

a set of routers, wherein each processing core in the set of processing cores includes at least one router from the set of routers;

wherein the set of programmable controllers execute the instructions in response to the set of routers exchanging the data for the complex computation.

4. The system of claim 3 , further comprising:

a set of dedicated hardware components for executing the application data flow graph, wherein the programmable controllers in the set of programmable controllers are components of the set of dedicated hardware components;

wherein the set of programmable controllers execute the instructions in response to the set of dedicated hardware components receiving events that indicate the set of routers have exchanged the data for the complex computation.

5. The system of claim 4 , further comprising:

a set of network interface modules, wherein each processing cores in the set of processing cores includes at least one network interface module from the set of network interface modules; and

a set of translator modules, wherein the translator modules are configured to translate inbound data transfers from the set of network interface modules to the events for the set of dedicated hardware components.

6. The system of claim 1 , wherein:

the core controllers in the set of core controllers are servants of the programmable controllers in the set of programmable controllers after the set of programmable controllers have been programmed with the instructions.

7. The system of claim 1 , wherein:

the programmable controllers in the set of programmable controllers are configured to control at least one of: (i) a stalled status; and (ii) a program counter of the core controllers in the set of core controllers.

8. The system of claim 1 , wherein:

the set of core controllers are part of a computation layer of the set of processing cores; and

the set of programmable controllers execute the instructions to administrate a streaming transfer of the data for the complex computation through a network layer of the set of processing cores.

9. The system of claim 8 , further comprising:

a set of network overlay units, wherein each processing core in the set of processing cores includes at least one network overlay unit from the set of network overlay units; and

the set of programmable controllers are part of the set of network overlay units;

wherein: (i) the set of network overlay units are part of a network overlay layer of the set of processing cores; and (ii) the network overlay layer logically isolates the computation layer from the network layer.

10. The system of claim 9 , wherein:

the programmable controllers in the set of programmable controllers have a customized instructions set for implementing the network overlay layer.

11. The system of claim 1 , wherein:

the programmable controllers in the set of programmable controllers are configured to be reconfigured with additional instructions during the execution of the application data flow graph to administrate additional transfers of data.

12. The system of claim 1 , wherein:

both the set of core controllers and the set of programmable controllers administrate transfers of data from the set of static random-access memories.

13. The system of claim 1 , further comprising:

a network for routing the data between the processing cores, wherein the network is a toroidal mesh;

wherein the programmable controllers are configured to administrate single-hop and multi-hop transmissions through the network.

14. A method for executing a complex computation on a set of processing cores, wherein the set of processing cores includes a set of processing pipelines, a set of static random-access memories, a set of core controllers, and a set of programmable controllers, wherein the set of programmable controllers are programmable stream controllers, and wherein the method comprises:

administrating, using the set of core controllers, transfers of data from the set of static random-access memories to the set of processing pipelines to execute a set of component computations required for the complex computation;

configuring the set of programmable controllers using instructions;

streaming the data for the complex computation between the processing cores in the set of processing cores; and

executing the instructions to execute an application data flow graph required for the complex computation;

wherein the application data flow graph requires data for the complex computation to flow between the processing cores in the set of processing cores.

15. The method of claim 14 , wherein:

the set of programmable controllers execute the instructions independently of the set of core controllers.

16. The method of claim 14 , further comprising:

exchanging the data for the complex computation between a set of routers, wherein each processing core in the set of processing cores includes at least one router from the set of routers;

wherein the set of programmable controllers execute the instructions in response to the set of routers exchanging the data for the complex computation.

17. The method of claim 16 , further comprising:

receiving, using a set of dedicated hardware components, events that indicate the set of routers have exchanged the data for the complex computation, wherein the programmable controllers in the set of programmable controllers are components of the set of dedicated hardware components;

wherein the set of programmable controllers execute the instructions in response to the set of dedicated hardware components receiving the events.

18. The method of claim 17 , further comprising:

translating inbound data transfers from a set of network interface modules to the events for the set of dedicated hardware components, wherein each processing cores in the set of processing cores includes at least one network interface module from the set of network interface modules.

19. The method of claim 14 , wherein:

the core controllers in the set of core controllers are servants of the programmable controllers in the set of programmable controllers after the set of programmable controllers have been programmed with the instructions.

20. The method of claim 14 , further comprising:

controlling, using the set of programmable controllers, at least one of: (i) a stalled status; and (ii) a program counter of the core controllers in the set of core controllers.

21. The method of claim 14 , wherein:

the core controllers in the set of core controllers are part of a computation layer of the set of processing cores; and

the programmable controllers in the set of programmable controllers execute the instructions to administrate a streaming transfer of the data for the complex computation through a network layer of the set of processing cores.

22. The method of claim 21 , further comprising:

logically isolating the computation layer from the network layer using a network overlay layer;

wherein: (i) each processing core in the set of processing cores includes at least one network overlay unit from a set of network overlay units; (ii) the programmable controllers in the set of programmable controllers are part of the network overlay units in the set of network overlay units; and (iii) the set of network overlay units are part of the network overlay layer.

23. The method of claim 22 , wherein:

the programmable controllers in the set of programmable controllers have a customized instructions set for implementing the network overlay layer.

24. The method of claim 14 , further comprising:

reconfiguring the programmable controllers in the set of programmable controllers with additional instructions during the execution of the application data flow graph to administrate additional transfers of data.

25. The method of claim 14 , further comprising:

administrating transfers of the data from the set of static random-access memories using the set of core controllers; and

administrating transfers of the data from the set of static random-access memories using the set of programmable controllers.

26. The method of claim 14 , further comprising:

administrating, using the programmable controllers, single-hop and multi-hop transmissions through a network for routing the data between the processing cores;

wherein the network is a toroidal mesh.

27. A system for executing a complex computation on a set of processing cores, the system comprising:

a set of processing pipelines, wherein each processing core in the set of processing cores includes at least one processing pipeline from the set of processing pipelines;

a set of static random-access memories, wherein each processing core in the set of processing cores includes at least one static random-access memory from the set of static random-access memories;

a set of core controllers to administrate transfers of data from the set of static random-access memories to the set of processing pipelines to execute a set of component computations required for the complex computation, wherein each processing core in the set of processing cores includes at least one core controller from the set of core controllers;

a set of programmable controllers, wherein the programmable controllers in the set of programmable controllers are configurable using instructions, wherein the set of programmable controllers execute the instructions to execute an application data flow graph required for the complex computation, each processing core in the set of processing cores includes at least one programmable controller from the set of programmable controllers, and the application data flow graph requires data for the complex computation to flow between the processing cores in the set of processing cores;

a set of routers, wherein each processing core in the set of processing cores includes at least one router from the set of routers, and the set of programmable controllers execute the instructions in response to the set of routers exchanging the data for the complex computation;

a set of dedicated hardware components for executing the application data flow graph, wherein the programmable controllers in the set of programmable controllers are components of the set of dedicated hardware components, and wherein the set of programmable controllers execute the instructions in response to the set of dedicated hardware components receiving events that indicate the set of routers have exchanged the data for the complex computation;

a set of network interface modules, wherein each processing cores in the set of processing cores includes at least one network interface module from the set of network interface modules; and

a set of translator modules, wherein the translator modules are configured to translate inbound data transfers from the set of network interface modules to the events for the set of dedicated hardware components.

28. A system for executing a complex computation on a set of processing cores, the system comprising:

a set of processing pipelines, wherein each processing core in the set of processing cores includes at least one processing pipeline from the set of processing pipelines;

a set of static random-access memories, wherein each processing core in the set of processing cores includes at least one static random-access memory from the set of static random-access memories;

a set of core controllers to administrate transfers of data from the set of static random-access memories to the set of processing pipelines to execute a set of component computations required for the complex computation, wherein each processing core in the set of processing cores includes at least one core controller from the set of core controllers and the set of core controllers are part of a computation layer of the set of processing cores; and

a set of programmable controllers, wherein the programmable controllers in the set of programmable controllers are configurable using instructions, wherein the set of programmable controllers execute the instructions to administrate a streaming transfer of the data for the complex computation through a network layer of the set of processing cores and execute the instructions to execute an application data flow graph required for the complex computation, and wherein each processing core in the set of processing cores includes at least one programmable controller from the set of programmable controllers;

wherein the application data flow graph requires data for the complex computation to flow between the processing cores in the set of processing cores.

29. The system of claim 28 , further comprising:

a set of network overlay units, wherein each processing core in the set of processing cores includes at least one network overlay unit from the set of network overlay units; and

the set of programmable controllers are part of the set of network overlay units;

wherein: (i) the set of network overlay units are part of a network overlay layer of the set of processing cores; and (ii) the network overlay layer logically isolates the computation layer from the network layer.

30. The system of claim 29 , wherein:

the programmable controllers in the set of programmable controllers have a customized instructions set for implementing the network overlay layer.

31. A method for executing a complex computation on a set of processing cores, wherein the set of processing cores includes a set of processing pipelines, a set of static random-access memories, a set of core controllers, and a set of programmable controllers, and wherein the method comprises:

administrating, using the set of core controllers, transfers of data from the set of static random-access memories to the set of processing pipelines to execute a set of component computations required for the complex computation;

configuring the set of programmable controllers using instructions;

exchanging the data for the complex computation between a set of routers, wherein each processing core in the set of processing cores includes at least one router from the set of routers, and wherein the set of programmable controllers execute the instructions in response to the set of routers exchanging the data for the complex computation;

receiving, using a set of dedicated hardware components, events that indicate the set of routers have exchanged the data for the complex computation, wherein the programmable controllers in the set of programmable controllers are components of the set of dedicated hardware components, wherein the set of programmable controllers execute the instructions in response to the set of dedicated hardware components receiving the events;

translating inbound data transfers from a set of network interface modules to the events for the set of dedicated hardware components, wherein each processing core in the set of processing cores includes at least one network interface module from the set of network interface modules; and

executing the instructions to execute an application data flow graph required for the complex computation, wherein the application data flow graph requires data for the complex computation to flow between the processing cores in the set of processing cores.

32. A method for executing a complex computation on a set of processing cores, wherein the set of processing cores includes a set of processing pipelines, a set of static random-access memories, a set of core controllers, and a set of programmable controllers, wherein the core controllers in the set of core controllers are part of a computation layer of the set of processing cores, and wherein the method comprises:

administrating, using the set of core controllers, transfers of data from the set of static random-access memories to the set of processing pipelines to execute a set of component computations required for the complex computation;

configuring the set of programmable controllers using instructions; and

executing the instructions to execute an application data flow graph required for the complex computation, wherein the programmable controllers in the set of programmable controllers execute the instructions to administrate a streaming transfer of the data for the complex computation through a network layer of the set of processing cores;

wherein the application data flow graph requires data for the complex computation to flow between the processing cores in the set of processing cores.

33. The method of claim 32 , further comprising:

logically isolating the computation layer from the network layer using a network overlay layer;

wherein: (i) each processing core in the set of processing cores includes at least one network overlay unit from a set of network overlay units; (ii) the programmable controllers in the set of programmable controllers are part of the network overlay units in the set of network overlay units; and (iii) the set of network overlay units are part of the network overlay layer.

34. The method of claim 33 , wherein:

the programmable controllers in the set of programmable controllers have a customized instructions set for implementing the network overlay layer.

Assignments (3)
CHANGE OF NAME Recorded Feb 23, 2025
From: TENSTORRENT INC.
To: TENSTORRENT AI INC.
Reel/Frame 070298/0922 →
CHANGE OF NAME Recorded Feb 23, 2025
From: TENSTORRENT AI INC.
To: TENSTORRENT AI ULC
Reel/Frame 070298/0944 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2023
From: MATOSEVIC, IVAN; CAPALIJA, DAVOR; VASILJEVIC, JASMINA; AYDONAT, UTKU; CHIN, S. ALEXANDER; MAKSIMOVIC, DJORDJE; BAJIC, LJUBISA
To: TENSTORRENT INC.
Reel/Frame 063623/0460 →
Continuity (2)
Continuation 17035046 · Sep 28, 2020
Related Publication 20230281155A1 · Sep 7, 2023
References Cited (20)
US 7882277B2 · Todaka · 2011 [cited by examiner]
US 10380063B2 · Tang et al. · 2019 [cited by applicant]
US 10616045B2 · Dubey et al. · 2020 [cited by applicant]
US 10628622B1 · Sivaraman et al. · 2020 [cited by applicant]
US 11227086B2 · Boesch et al. · 2022 [cited by applicant]
US 20080005402A1 · Kim et al. · 2008 [cited by applicant]
US 20080181115A1 · Soulie et al. · 2008 [cited by applicant]
US 20090260013A1 · Heil · 2009 [cited by examiner]
US 20140355449A1 · Tokuoka · 2014 [cited by applicant]
US 20170185449A1 · Zhang · 2017 [cited by examiner]
US 20190018815A1 · Fleming et al. · 2019 [cited by applicant]
US 20190303153A1 · Halpern · 2019 [cited by examiner]
US 20200174849A1 · Yang et al. · 2020 [cited by applicant]
US 20230251994A1 · Shah · 2023 [cited by examiner]
CN 101778049A · 2010 [cited by applicant]
WO 2020061888A1 · 2020 [cited by applicant]
Final Office Action from U.S. Appl. No. 17/035,046 dated Jun. 28, 2022, 14 pages. [cited by applicant]
Non-Final Office Action dated Feb. 4, 2022 from U.S. Appl. No. 17/035,046, 21 pages. [cited by applicant]
Notice of allowance from U.S. Appl. No. 17/035,046 dated Mar. 21, 2023, 9 pages. [cited by applicant]
Schor et al., “Scenario-Based Design Flow for Mapping Streaming Applications onto On-Chip Many-Core Systems”, CASES'12, Oct. 7-12, 2012, Tampere, Finland, pp. 71-80. [cited by applicant]