IP Library Granted Patent US 11,977,444
Granted Patent B2
US 11,977,444 · App. 18/200,439 · Granted May 7, 2024

Methods for error count reporting with scaled error count information, and memory devices employing the same

Inventors: Matthew A. Prather (Boise, ID); Randall J. Rooney (Boise, ID)
G06F11/1068G06F11/076G11C13/0026G11C13/0028G06F2201/88
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Quick Facts
Patent No.
US 11,977,444
App. No.
18/200,439
Granted
May 7, 2024
Kind
B2
Abstract

An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.

Claims (69)

1. An apparatus, comprising:

a memory array; and

a controller coupled with the memory array and configured to cause the apparatus to:

perform an error control operation at the memory array;

identify a quantity of errors associated with the memory array based at least in part on performing the error control operation;

compare the quantity of errors to one or more threshold values;

determine a scaled value based at least in part on comparing the quantity of errors to the one or more threshold values; and

store the scaled value in a mode register associated with the memory array.

2. The apparatus of claim 1 , wherein the controller is configured to cause the apparatus to:

scale the quantity of errors with a logarithmic scale or a linear scale to generate the scaled value, wherein determining the scaled value is based at least in part on scaling the quantity of errors.

3. The apparatus of claim 1 , wherein to compare the quantity of errors to the one or more threshold values, the controller is configured to cause the apparatus to:

compare the quantity of errors to a first threshold value; and

compare the quantity of errors to a second threshold value greater than the first threshold value,

wherein determining the scaled value is based at least in part on identifying that the quantity of errors is greater than the first threshold value and less than the second threshold value.

4. The apparatus of claim 1 , wherein the controller is configured to cause the apparatus to:

receive an indication comprising the one or more threshold values; and

store the indication in the mode register, wherein comparing the quantity of errors to the one or more threshold values is based at least in part on accessing the mode register.

5. The apparatus of claim 1 , wherein the error control operation comprises an error check and scrub (ECS) operation, wherein the controller is configured to cause the apparatus to:

read, as part of the ECS operation, data associated with a plurality of codewords stored in the memory array,

wherein identifying the quantity of errors is based at least in part on identifying a quantity of codewords that include data with one or more errors.

6. The apparatus of claim 1 , wherein the error control operation comprises an error check and scrub (ECS) operation, wherein the controller is configured to cause the apparatus to:

read, as part of the ECS operation, data from a plurality of rows of the memory array,

wherein identifying the quantity of errors is based at least in part on identifying a quantity of rows that include data with one or more errors.

7. The apparatus of claim 1 , wherein the controller is configured to cause the apparatus to:

determine that the quantity of errors satisfies an initial threshold, wherein comparing the quantity of errors to the one or more threshold values is based at least in part on determining that the quantity of errors satisfies the initial threshold.

8. A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:

perform an error control operation at a memory array;

identify a quantity of errors associated with the memory array based at least in part on performing the error control operation;

compare the quantity of errors to one or more threshold values;

determine a scaled value based at least in part on comparing the quantity of errors to the one or more threshold values; and

store the scaled value in a mode register associated with the memory array.

9. The non-transitory computer-readable medium of claim 8 , wherein the instructions are further executable by the one or more processors to:

scale the quantity of errors with a logarithmic scale or a linear scale to generate the scaled value, wherein determining the scaled value is based at least in part on scaling the quantity of errors.

10. The non-transitory computer-readable medium of claim 8 , wherein the instructions to compare the quantity of errors to the one or more threshold values are executable by the one or more processors to:

compare the quantity of errors to a first threshold value; and

compare the quantity of errors to a second threshold value greater than the first threshold value,

wherein determining the scaled value is based at least in part on identifying that the quantity of errors is greater than the first threshold value and less than the second threshold value.

11. The non-transitory computer-readable medium of claim 8 , wherein the instructions are further executable by the one or more processors to:

receive an indication comprising the one or more threshold values; and

store the indication in the mode register, wherein comparing the quantity of errors to the one or more threshold values is based at least in part on accessing the mode register.

12. The non-transitory computer-readable medium of claim 8 , wherein the error control operation comprises an error check and scrub (ECS) operation comprising:

reading, as part of the ECS operation, data associated with a plurality of codewords stored in the memory array,

wherein identifying the quantity of errors is based at least in part on identifying a quantity of codewords that include data with one or more errors.

13. The non-transitory computer-readable medium of claim 8 , wherein the error control operation comprises an error check and scrub (ECS) operation comprising:

reading, as part of the ECS operation, data from a plurality of rows of the memory array,

wherein identifying the quantity of errors is based at least in part on identifying a quantity of rows that include data with one or more errors.

14. The non-transitory computer-readable medium of claim 8 , wherein the instructions are further executable by the one or more processors to:

determining that the quantity of errors satisfies an initial threshold, wherein comparing the quantity of errors to the one or more threshold values is based at least in part on determining that the quantity of errors satisfies the initial threshold.

15. A method, comprising:

performing an error control operation at a memory array;

identifying a quantity of errors associated with the memory array based at least in part on performing the error control operation;

comparing the quantity of errors to one or more threshold values;

determining a scaled value based at least in part on comparing the quantity of errors to the one or more threshold values; and

storing the scaled value in a mode register associated with the memory array.

16. The method of claim 15 , further comprising:

scaling the quantity of errors with a logarithmic scale or a linear scale to generate the scaled value, wherein determining the scaled value is based at least in part on scaling the quantity of errors.

17. The method of claim 15 , wherein comparing the quantity of errors to the one or more threshold values comprises:

comparing the quantity of errors to a first threshold value; and

comparing the quantity of errors to a second threshold value greater than the first threshold value,

wherein determining the scaled value is based at least in part on identifying that the quantity of errors is greater than the first threshold value and less than the second threshold value.

18. The method of claim 15 , further comprising:

receiving an indication comprising the one or more threshold values; and

storing the indication in a threshold storage location, wherein comparing the quantity of errors to the one or more threshold values is based at least in part on accessing the threshold storage location.

19. The method of claim 15 , wherein the error control operation comprises an error check and scrub (ECS) operation comprising:

reading, as part of the ECS operation, data associated with a plurality of codewords stored in the memory array,

wherein identifying the quantity of errors is based at least in part on identifying a quantity of codewords that include data with one or more errors.

20. The method of claim 15 , wherein the error control operation comprises an error check and scrub (ECS) operation comprising:

reading, as part of the ECS operation, data from a plurality of rows of the memory array,

wherein identifying the quantity of errors is based at least in part on identifying a quantity of rows that include data with one or more errors.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2025
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 071087/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2024
From: PRATHER, MATTHEW A.; ROONEY, RANDALL J.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 066485/0993 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2024
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 066484/0485 →