ESD protection apparatus and control method
An ESD protection apparatus includes a first clamping device and a second clamping device connected in series between a bias voltage bus and ground, and a switch coupled between an input/output pad and a common node of the first clamping device and the second clamping device, wherein the switch is configured such that before a bias voltage on the bias voltage bus has been established, a leakage current flowing through the first clamping device is reduced.
1. An apparatus comprising:
a first clamping device and a second clamping device connected in series between a bias voltage bus and ground;
a switch coupled between an input/output pad and a common node of the first clamping device and the second clamping device, wherein the switch is configured such that before a bias voltage on the bias voltage bus has been established, a leakage current flowing through the first clamping device is reduced;
a low-dropout regulator configured to provide the bias voltage, wherein the low-dropout regulator is controlled by an enable signal;
a load coupled to the bias voltage bus; and
a buffer having an input connected to the common node of the first clamping device and the second clamping device.
2. The apparatus of claim 1 , wherein:
the first clamping device is a p-type transistor, and wherein:
a source terminal of the p-type transistor is connected to the bias voltage bus;
a body terminal of the p-type transistor is connected to the bias voltage bus;
a gate terminal of the p-type transistor is connected to the bias voltage bus; and
a drain terminal of the p-type transistor is connected to the second clamping device; and
the second clamping device is an n-type transistor, and wherein:
a source terminal of the n-type transistor is connected to ground;
a body terminal of the n-type transistor is connected to ground;
a gate terminal of the n-type transistor is connected to ground; and
a drain terminal of the n-type transistor is connected to the first clamping device.
3. The apparatus of claim 2 , wherein:
the p-type transistor functions as a first clamping diode; and
the n-type transistor functions as a second clamping diode, and wherein:
a cathode of the first clamping diode is connected to the bias voltage bus;
an anode of the first clamping diode is connected to a cathode of the second clamping diode; and
an anode of the second clamping diode is connected to ground.
4. The apparatus of claim 1 , further comprising:
a first resistor connected between the switch and the common node of the first clamping device and the second clamping device; and
a second resistor connected between the switch and the input/output pad.
5. The apparatus of claim 1 , further comprising:
a grounded-gate n-type transistor connected between the input/output pad and ground, wherein:
a source terminal of the grounded-gate n-type transistor is connected to ground;
a body terminal of the grounded-gate n-type transistor is connected to ground;
a gate terminal of the grounded-gate n-type transistor is connected to ground; and
a drain terminal of the grounded-gate n-type transistor is connected to the input/output pad.
6. The apparatus of claim 1 , further comprising:
a delay control unit configured to receive the enable signal and the bias voltage, and generate a gate drive signal for controlling the switch; and
a filter having an input coupled to an output of the delay control unit and an output configured to generate the gate drive signal applied to the switch.
7. A method comprising:
providing a switch coupled between an input/output pad and a common node of a first clamping device and a second clamping device, wherein the first clamping device and the second clamping device are connected in series between a bias voltage bus and ground, and wherein a low-dropout regulator is configured to provide a bias voltage on the bias voltage bus, and wherein the low-dropout regulator is controlled by an enable signal, a load is coupled to the bias voltage bus; and a buffer has an input connected to the common node of the first clamping device and the second clamping device;
prior to establishing a bias voltage on the bias voltage bus, configuring the switch to reduce a leakage current flowing through the first clamping device; and
turning on the switch after the bias voltage has been established.
8. The method of claim 7 , further comprising:
turning on the switch after receiving a system command.
9. The method of claim 8 , further comprising:
generating, by the low-dropout regulator, the bias voltage at a first time instant once receiving the enable signal; and
after a predetermined delay from the first time instant, turning on the switch at a second time instant.
10. The method of claim 7 , further comprising:
generating, by the low-dropout regulator, the bias voltage at a first time instant once receiving the enable signal; and
from the first time instant to a second time instant, increasing a gate voltage of the switch in a linear manner from a first predetermined voltage to a second predetermined voltage.
11. The method of claim 7 , further comprising:
generating, by the low-dropout regulator, the bias voltage at a first time instant once receiving the enable signal; and
after a predetermined delay from the first time instant, increasing a gate voltage of the switch from a first predetermined voltage to a second predetermined voltage at a second time instant.
12. The method of claim 7 , further comprising:
generating, by the low-dropout regulator, the bias voltage at a first time instant once receiving the enable signal; and
prior to feeding the enable signal to the low-dropout regulator, increasing a gate voltage of the switch in a linear manner from a first predetermined voltage until the gate voltage reaches a second predetermined voltage at a second time instant.
13. The method of claim 12 , wherein:
the gate voltage of the switch is increased before the enable signal is applied to the low-dropout regulator; and
after a predetermined delay from the first time instant, the gate voltage of the switch reaches the second predetermined voltage.
14. The method of claim 7 , further comprising:
turning on the switch after the bias voltage is greater than or equal to a voltage on the input/output pad.
15. The method of claim 7 , wherein:
the switch, the first clamping device and the second clamping device are in a semiconductor chip, and wherein the semiconductor chip further comprises:
a first resistor connected between the switch and the common node of the first clamping device and the second clamping device;
a second resistor connected between the switch and the input/output pad;
a grounded-gate n-type transistor connected between the input/output pad and ground;
a delay control unit configured to receive the enable signal and the bias voltage; and
a filter having an input coupled to an output of the delay control unit, and an output configured to generate a gate drive signal for controlling the switch.
16. The method of claim 15 , wherein:
the first clamping device is a p-type transistor, and wherein:
a source terminal of the p-type transistor is connected to the bias voltage bus;
a body terminal of the p-type transistor is connected to the bias voltage bus;
a gate terminal of the p-type transistor is connected to the bias voltage bus; and
a drain terminal of the p-type transistor is connected to the second clamping device; and
the second clamping device is an n-type transistor, and wherein:
a source terminal of the n-type transistor is connected to ground;
a body terminal of the n-type transistor is connected to ground;
a gate terminal of the n-type transistor is connected to ground; and
a drain terminal of the n-type transistor is connected to the first clamping device.
17. An integrated circuit comprising:
a first clamping device and a second clamping device connected in series between a bias voltage bus and ground;
a switch coupled between an input/output pad and a common node of the first clamping device and the second clamping device;
a low-dropout regulator configured to provide a bias voltage on the bias voltage bus, wherein the low-dropout regulator is controlled by an enable signal; and
a load coupled to the bias voltage bus, and a buffer having an input connected to the common node of the first clamping device and the second clamping device, wherein the switch is controlled to prevent a leakage current from flowing from the input/output pad to the load.
18. The integrated circuit of claim 17 , wherein:
prior to establishing the bias voltage, the switch is turned off to prevent the leakage current from flowing from the input/output pad to the load; and
after establishing the bias voltage, the switch is turned on.
19. The integrated circuit of claim 17 , further comprising:
a first resistor connected between the switch and the common node of the first clamping device and the second clamping device;
a second resistor connected between the switch and the input/output pad;
a grounded-gate n-type transistor connected between the input/output pad and ground;
a delay control unit configured to receive the enable signal and the bias voltage; and
a filter having an input coupled to an output of the delay control unit, and an output configured to generate a gate drive signal for controlling the switch.