Error detection and checking in wireless communication systems
A device capable of operating in a wireless communication environment. The device may be configured to determine a plurality of control signaling bits. The device may determine a plurality of cyclic redundancy check (CRC) bits based on the plurality of control signaling bits. The device may apply a channel coding scheme to the plurality of control signaling bits and the plurality of CRC bits. The plurality of CRC bits may be distributed among the plurality of control signaling bits prior to applying the channel coding scheme. The device may transmit the channel coded plurality of control signaling bits and CRC bits.
1. A device capable of operating in a wireless communication environment, the device comprising a processor configured to:
determine a plurality of control signaling bits;
determine a plurality of cyclic redundancy check (CRC) bits based on the plurality of control signaling bits;
generate a bitstream to which a channel coding scheme is to be applied, wherein the bitstream is ordered for channel coding such that a first portion of the control signaling bits precedes a first portion of the plurality of CRC bits, the first portion of the plurality CRC bits precedes a second portion of the control signaling bits, and the second portion of the control signaling bits precedes a second portion of the plurality of CRC bits;
apply the channel coding scheme to the bitstream in accordance with the ordering applied prior to channel coding; and
transmit the channel coded bitstream.
2. The device of claim 1 , wherein the plurality of control signaling bits comprise a plurality of groups of precoding matrix index (PMI) bits.
3. The device of claim 2 , wherein the plurality of CRC bits comprise a respective set of one or more CRC bits for each of the plurality of groups of PMI bits.
4. The device of claim 3 , wherein the first portion of the control signaling bits comprises a first group of PMIs, the first portion of the plurality of CRC bits comprises first CRC bits attached to an end of the first group of PMIs, the second portion of the control signaling bits comprises a second group of PMIs, and the second portion of the control signaling bits comprises second CRC bits attached to an end of the second group of PMIs.
5. The device of claim 1 , wherein the channel coded bitstream is transmitted over a control channel.
6. A device capable of operating in a wireless communication environment, the device comprising a processor configured to:
receive channel coded bits;
decode the channel coded bits to determine a decoded bitstream, wherein the decoded bitstream is ordered such that a first portion of control signaling bits precedes a first portion of a plurality of cyclic redundancy check (CRC) bits, the first portion of the plurality CRC bits precedes a second portion of the control signaling bits, and the second portion of the control signaling bits precedes a second portion of the plurality of CRC bits; and
determine if any errors are present in the plurality of control signaling bits based on the plurality of CRC bits.
7. The device of claim 6 , wherein the plurality of control signaling bits comprise a plurality of groups of precoding matrix index (PMI) bits.
8. The device of claim 7 , wherein the plurality of CRC bits comprise a respective set of one or more CRC bits for each of the plurality of groups of PMI bits.
9. The device of claim 8 , wherein the first portion of the control signaling bits comprises a first group of PMIs, the first portion of the plurality of CRC bits comprises first CRC bits attached to an end of the first group of PMIs, the second portion of the control signaling bits comprises a second group of PMIs, and the second portion of the control signaling bits comprises second CRC bits attached to an end of the second group of PMIs.
10. The device of claim 6 , wherein the channel coded bits received over a control channel.
11. A method comprising:
receiving channel coded bits;
decoding the channel coded bits to determine a decoded bitstream, wherein the decoded bitstream is ordered such that a first portion of control signaling bits precedes a first portion of a plurality of cyclic redundancy check (CRC) bits, the first portion of the plurality CRC bits precedes a second portion of the control signaling bits, and the second portion of the control signaling bits precedes a second portion of the plurality of CRC bits; and
determining if any errors a present in the plurality of control signaling bits based on the plurality of CRC bits.
12. The method of claim 11 , wherein the plurality of control signaling bits comprise a plurality of groups of precoding matrix index (PMI) bits.
13. The method of claim 12 , wherein the plurality of CRC bits comprise a respective set of one or more CRC bits for each of the plurality of groups of PMI bits.
14. The method of claim 13 , wherein the first portion of the control signaling bits comprises a first group of PMIs, the first portion of the plurality of CRC bits comprises first CRC bits attached to an end of the first group of PMIs, the second portion of the control signaling bits comprises a second group of PMIs, and the second portion of the control signaling bits comprises second CRC bits attached to an end of the second group of PMIs.
15. The method of claim 11 , wherein the channel coded bits received over a control channel.