IP Library Granted Patent US 12,040,423
Granted Patent B2
US 12,040,423 · App. 18/202,037 · Granted Jul 16, 2024

Methods of making flip chip micro light emitting diodes

Inventors: Yeow Meng Teo (Singapore, SG); Wee-Hong Ng (Singapore, SG); Pei-Chee Mah (Singapore, SG); Chee Chung James Wong (Singapore, SG); Geok Joo Soh (Singapore, SG)
Assignee: Lumileds LLC
H01L33/007H01L25/0753H01L33/0093H01L33/0095H01L2933/0016H01L2933/0025H01L2933/005H01L2933/0066
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Quick Facts
Patent No.
US 12,040,423
App. No.
18/202,037
Granted
Jul 16, 2024
Kind
B2
Abstract

A micro-light emitting diode (uLED) device comprises: a mesa comprising: a plurality of semiconductor layers including an n-type layer, an active layer, and a p-type layer; a p-contact layer contacting the p-type layer; a cathode contacting the first sidewall of the n-type layer; a first region of dielectric material that insulates the p-contact layer, the active layer, and a first sidewall of the p-type layer from the cathode; an anode contacting the top surface of the p-contact layer; and a second region of dielectric material that insulates the active layer, a second sidewall of the p-type layer, and the second sidewall of the n-type layer from the anode. The top surface of the p-contact layer has a different planar orientation compared to the first and second sidewalls of the n-type layer. Methods of making and using the uLED devices are also provided.

Claims (29)

1. A method of manufacturing a micro-light emitting diode (uLED) device comprising:

first etching a substrate comprising trenches and a plurality of mesas layered with one or more dielectric materials to expose p-contact layers of the mesas and first portions of a surface of the substrate, the mesas comprising respective n-type layers, active layers, p-type layers, and the p-contact layers on the p-type layers, and having widths spanning first sidewalls of the n-type layers to second sidewalls of the n-type layers, and heights spanning from top surfaces of the p-contact layers to bottom surfaces of the n-type layers;

second etching the substrate to expose the n-type layers and second portions of the surface of the substrate;

depositing an electrode metal onto areas exposed by the first etching and the second etching;

further etching to form cathodes and anodes from the electrode metal, which are isolated from each other;

the foregoing steps forming a processed structure.

2. The method of claim 1 , wherein the cathodes and anodes longitudinally span at least the heights of the mesas.

3. The method of claim 1 , wherein portions of the cathodes are positioned above the top surfaces of the respective p-contact layers.

4. The method of claim 1 , wherein the widths of the mesas are less than 100 micrometers.

5. The method of claim 1 , wherein heights of the mesas are less than or equal to the widths of the mesas.

6. The method of claim 1 comprising conducting a masking prior to the first etching to expose the p-contact layer.

7. The method of claim 1 , wherein two planar orientations of the p-contact layer are exposed during the first etching to expose the p-contact layer.

8. The method of claim 1 , wherein two planar orientations of the n-layer are exposed during the second etching to expose the n-layer.

9. The method of claim 1 comprising conducting a masking prior to the second etching to expose the n-type layer.

10. The method of claim 1 comprising forming a passivation layer on the processed structure.

11. The method of claim 1 comprising singulating the mesas to form individual uLEDs.

12. The method of claim 11 comprising adhering bonding surfaces of the cathodes and the anodes of the processed structure to a support; removing the substrate; and thereafter singulating the mesas to form individual uLEDs.

13. The method of claim 1 , wherein the n-type layer comprises N-GaN and the p-type layer comprises P-GaN.

14. The method of claim 1 , wherein a first region of dielectric material insulates the p-contact layer, the active layer, and a first sidewall of the p-type layer from the cathode, and a second region of dielectric material insulates the active layer, a second sidewall of the p-type layer, and the second sidewall of the n-type layer from the anode; and the dielectric material of the first region and of the second region independently each comprise a material selected from the group consisting of SiO 2 , AlO x , and SiN, each independently has a thickness in a range of from 200 nm to 1 μm.

15. The method of claim 1 , wherein the p-contact layer contacting the p-type layer substantially spans a width of the p-type layer.

16. The method of claim 1 , wherein the p-type layer substantially spans a width of the active layer.

17. The method of claim 1 , wherein the uLEDs are effective as flip chip light emitting diodes.

18. A method of making a display system comprising:

preparing a light emitting array by a pick-and-place method of a plurality of micro light emitting diodes (uLEDs) made according to claim 11 ;

enclosing the plurality of uLEDs in a housing with a display face; and

electrically connecting the uLEDs to a driver integrated circuit;

the plurality of uLEDs or groups of the uLEDs being independently controllable.

19. The method of claim 18 , wherein the uLEDs have one or more characteristic dimensions of less than 100 micrometers.

20. The method of claim 19 , wherein the dimensions are in a range of greater than or equal to 2 micrometers to less than or equal to 25 micrometers.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2025
From: LUMILEDS LLC
To: LUMILEDS SINGAPORE PTE. LTD.
Reel/Frame 071888/0086 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2023
From: TEO, YEOW MENG; NG, WEE-HONG; MAH, PEI-CHEE; WONG, CHEE CHUNG JAMES; SOH, GEOK JOO
To: LUMILEDS LLC
Reel/Frame 063765/0303 →