Granted Patent B2

US 12,277,067 · App. 18/203,143 · Granted Apr 15, 2025

Inventor: Perry V. Lea (Plano, TX)

G06F12/1009G06F12/0864G06F12/1027G06F12/1045G06F2212/1016G06F2212/1028G06F2212/651G06F2212/652G06F2212/684

Abstract

Claims (37)

1. An apparatus, comprising:

an array of memory cells;

sensing circuitry coupled to the array of memory cells; and

one or more compute components included in the array, the one or more compute components configured to:

perform a number of operations based at least in part on a physical address of a portion of data stored in the array, wherein the one or more compute components are configured to perform the number of operations in response to a command from a host, the command comprising an indication of the physical address associated with the portion of the data stored in the array;

use the physical address as an input to a table to obtain at least one result of the number of operations, wherein the table is associated with the array, and wherein the at least one result comprises a result of a respective logical operation; and

store the at least one result of the number of operations without transferring the at least one result outside the array.

2. The apparatus of claim 1 , wherein the apparatus is further configured to store the portion of data in a buffer, wherein the buffer is a translation lookaside buffer (TLB).

3. The apparatus of claim 1 , wherein the apparatus is configured to be used as a fully associative cache to determine the physical address.

4. The apparatus of claim 1 , wherein the apparatus is configured to, in response to the portion of data not being in the array of memory cells, indicate to the host to locate the portion of data in an additional memory location.

5. The apparatus of claim 1 , wherein the apparatus is configured to cause a page walk through a page table in the array independent of receiving intermediate instructions to perform the page table walk from the host.

6. The apparatus of claim 5 , wherein the apparatus is further configured to cause storing of a series of descriptors with tiered levels that indicate a location of the portion of data.

7. The apparatus of claim 6 , wherein each of the tiered levels is a pointer to a sub-section of a subsequent next level of the tiered levels.

8. The apparatus of claim 7 , wherein a final tiered level of the tiered levels indicates the physical address of the portion of data.

9. A method, comprising:

receiving, from a host device, a command comprising an indication of a physical address associated with data stored in an array of memory cells;

performing, by one or more compute components that are included in the array of memory cells, one or more operations in response to the command from the host device, wherein the one or more operations are performed based at least in part on the physical address associated with the data;

generating respective results of the one or more operations based at least in part on using the physical address as an input to a table associated with the array, each of the respective results comprising a result of a logical operation; and

storing the respective results of the one or more operations without transferring the respective results outside the array.

10. The method of claim 9 , wherein performing the one or more operations comprises:

performing a page table walk in the array to determine a physical address of the data, wherein performing the page table walk comprises resolving a first level of a page table in the array to determine a location in a second level of the page table.

11. The method of claim 10 , comprising:

resolving the second level to determine a location in a third level of the page table;

resolving the third level of the page table to determine a location in a fourth level of the page table; and

resolving the fourth level of the page table to determine the physical address corresponding to a virtual address of the data.

12. The method of claim 10 , wherein, in response to determining the physical address, sending a portion of data located at the physical address to be stored in a translation lookaside buffer (TLB).

13. The method of claim 10 , wherein performing the page table walk comprises comparing a virtual address with each of a plurality of elements of the page table simultaneously.

14. The method of claim 13 , wherein comparing the virtual address with each of the plurality of elements comprises comparing the virtual address with a first of the plurality of elements.

15. An apparatus, comprising:

an array of memory cells;

sensing circuitry coupled to the array of memory cells;

one or more compute components included in the array; and

a controller coupled to the one or more compute components and configured to control the one or more compute components to:

in response to a command from a host, perform a number of logical operations based at least in part on a physical address of a portion of data stored in the array, the command comprising an indication of the physical address associated with the portion of the data, wherein the one or more compute components are configured to use the physical address as an input to a table to obtain at least one result of the number of logical operations, wherein the table is associated with the array, and wherein the at least one result comprises a result of a respective logical operation; and

store the at least one result of the number of logical operations without transferring the at least one result outside the array.

16. The apparatus of claim 15 , wherein the physical address of the portion of data corresponds to a virtual address.

17. The apparatus of claim 16 , wherein the controller is configured to control the one or more compute components to perform a walk through of a page table, the walk through including resolving page table levels simultaneously by comparing the virtual address to each of a plurality of elements in the page table.

Assignments (2)

Continuity (4)

References Cited (373)