Granted Patent B2

US 12,211,101 · App. 18/207,281 · Granted Jan 28, 2025

Inventors: David E. Taylor (St. Louis, MO); Scott Parsons (St. Charles, MO); Jeremy Walter Whatley (Ballwin, MO); Richard Bradley (St. Louis, MO); Kwame Gyang (St. Louis, MO); Michael DeWulf (St. Louis, MO)

Assignee: Exegy Incorporated

G06Q40/04G06Q40/00

Abstract

Claims (27)

1. A system for applying specific computer technology to reduce latency and increase throughput with respect to updating a plurality of financial instrument order books in response to financial market data, the system comprising:

a memory for storing a plurality of order records and a plurality of price point records, wherein the order records define a plurality of order books for a plurality of financial instruments, and wherein the price point records define a plurality of price books for the financial instruments; and

a field programmable gate array (FPGA) for processing financial market data, wherein the processed financial market data includes a plurality of limit order events for a plurality of financial instruments, and wherein the FPGA is configured to (1) map the limit order events to applicable order records and price point records in the memory and (2) perform updates in parallel to the applicable order records and price point records based on the mapped limit order events.

2. The system of claim 1 wherein the FPGA is further configured to perform hashing in parallel on the limit order events to generate order hash keys and price hash keys for mapping the limit order events to their applicable order records and price point records.

3. The system of claim 2 wherein each of a plurality of the limit order events comprises a plurality of fields that hold data describing the limit order events, and wherein the FPGA is further configured to (1) generate, in parallel for each of a plurality of the limit order events, an applicable order hash key based on a first plurality of the fields and an applicable price hash key based on a second plurality of the fields, (2) map the limit order events to their applicable order records based the generated applicable order hash keys, and (3) map the limit order events to their applicable price point records based on the generated applicable price hash keys, wherein the first plurality of the fields is not the same as the second plurality of the fields.

4. The system of claim 3 wherein the first plurality of the fields comprises (1) a field that holds data indicative of a symbol for a subject limit order event, (2) a field that holds data indicative of an exchange for the subject limit order event, and (3) a field that holds data indicative of an order reference number for the subject limit order event.

5. The system of claim 4 wherein the second plurality of the fields comprises (1) the field that holds data indicative of the symbol for the subject limit order event, (2) the field that holds data indicative of the exchange for the subject limit order event, and (3) a field that holds data indicative of a price for the subject limit order event.

6. The system of claim 2 wherein the price point records comprise a plurality of regional price point records and a plurality of composite price point records, wherein the generated price hash keys comprise generated regional price aggregation keys and generated composite price aggregation keys, and wherein the FPGA is further configured to (1) map the limit order events to applicable regional price point records based on the generated regional price aggregation keys and (2) map the limit order events to applicable composite price point records based on the generated composite price aggregation keys.

7. The system of claim 1 wherein the FPGA comprises reconfigurable hardware logic that defines an order engine and a price engine that operate in parallel with each other, wherein the order engine is configured to update the applicable order records based on the mapped limit order events, and wherein the price engine is configured to update the applicable price point records based on the mapped limit order events.

8. The system of claim 7 wherein the order engine and the price engine are configured to interleave accesses to the memory to update the applicable limit order records and the applicable price point records.

9. The system of claim 1 wherein the FPGA is resident within a ticker plant, the ticker plant also including a processor, and wherein the FPGA is configured to serve as an offload engine relative to the processor.

10. The system of claim 1 wherein the FPGA is further configured to enrich limit order events within the processed financial market data with information derived from the accessed price point records, wherein the enriched limit order events are for delivery to a plurality of data consumers.

11. The system of claim 1 wherein the memory comprises a single physical memory in which a plurality of the order records and a plurality of the price point records are stored.

12. The system of claim 11 wherein the FPGA is further configured to interleave accesses to the single physical memory.

13. The system of claim 1 wherein the memory comprises a first physical memory in which a plurality of the order records are stored and a second physical memory in which a plurality of the price point records are stored.

14. The system of claim 13 wherein the FPGA is further configured to interleave accesses to the first and second physical memories.

15. The system of claim 1 wherein the memory is external to the FPGA; and

wherein the FPGA is further configured to (1) cache a plurality of accessed order records and a plurality of accessed price point records in an on-chip memory cache, (2) track which order records and which price point records are cached in the on-chip memory cache, (3) receive a subject limit order event pertaining to a cached order record and/or a cached price point record, (4) based on the tracking of which order records and price point records are cached in the on-chip memory cache, (i) access the order record pertaining to the received subject limit order event via the on-chip memory cache rather than the external memory and/or (ii) access the price point record pertaining to the received subject limit order event via the on-chip memory cache rather than the external memory.

16. The system of claim 15 wherein the on-chip memory cache comprises a first on-chip memory cache configured to cache accessed order records and a second on-chip memory cache configured to cache accessed price point records.

17. A system for applying specific computer technology to reduce latency and increase throughput with respect to updating a plurality of financial instrument order books in response to financial market data, the system comprising:

a memory for storing a plurality of order records and a plurality of price point records, wherein the order records define a plurality of order books for a plurality of financial instruments, and wherein the price point records define a plurality of price books for the financial instruments; and

a member of the group consisting of (1) a reconfigurable logic device, (2) a chip multi-processor (CMP), (3) an application-specific integrated circuit (ASIC), (4) a graphics processing unit (GPU), and (5) a multi-core superscalar processor, the member for processing financial market data, wherein the processed financial market data includes a plurality of limit order events for a plurality of financial instruments, and wherein the member is configured to (1) map the limit order events to applicable order records and price point records in the memory and (2) perform updates in parallel to the applicable order records and price point records based on the mapped limit order events.

18. The system of claim 17 wherein the member is further configured to perform hashing in parallel on the limit order events to generate order hash keys and price hash keys for mapping the limit order events to their applicable order records and price point records.

19. The system of claim 18 wherein each of a plurality of the limit order events comprises a plurality of fields that hold data describing the limit order events, and wherein the member is further configured to (1) generate, in parallel for each of a plurality of the limit order events, an applicable order hash key based on a first plurality of the fields and an applicable price hash key based on a second plurality of the fields, (2) map the limit order events to their applicable order records based the generated applicable order hash keys, and (3) map the limit order events to their applicable price point records based on the generated applicable price hash keys, wherein the first plurality of the fields is not the same as the second plurality of the fields.

20. A method for applying specific computer technology to reduce latency and increase throughput with respect to updating a plurality of financial instrument order books in response to financial market data, the method comprising:

storing a plurality of order records and a plurality of price point records in memory, wherein the order records define a plurality of order books for a plurality of financial instruments, and wherein the price point records define a plurality of price books for the financial instruments; and

processing financial market data by a member of the group consisting of (1) a reconfigurable logic device, (2) a chip multi-processor (CMP), (3) an application-specific integrated circuit (ASIC), (4) a graphics processing unit (GPU), and (5) a multi-core superscalar processor, wherein the processed financial market data includes a plurality of limit order events for a plurality of financial instruments, and wherein the processing step comprises the member (1) mapping the limit order events to applicable order records and price point records in the memory and (2) performing updates in parallel to the applicable order records and price point records based on the mapped limit order events.

Assignments (4)

Continuity (7)

References Cited (400)